Effect of Line Parasitic Variations on Delay and Energy of Global On-Chip VLSI Interconnects in DSM Technology

Venkataiah, C.; Satyaprasad, K.; Prasad, T. Jayachandra

doi:10.1007/978-981-10-4280-5_23

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Hence, increasing the amount of power dissipation in integrated circuits. Improvement in technology or scaling leads to provide a significant increase in parasitic interconnects wires [6][7][8][9][10][11][12]. The inductive effect and capacitive coupling effect give interconnect wire coupling crosstalk significance and cause many signal integrity problems.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

Venkataiah¹,

Setty²,

Ramanjaneyulu³

et al. 2023

International Journal of Emerging Research in Engineering, Science, and Management

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As technology extended from deep sub-micron technology to nanometer regimes, the conventional copper (Cu) wire will not be able to continue. Now a substitute approaches such as Carbon Nano Tube (CNT) interconnects have been suggested to ignore the problems associated with global interconnects. Hence in this work, crosstalk analysis of Complementary metal oxide semiconductor (CMOS) buffer-driven of different interconnects have been analyzed for peak overshoot and overshoot width of Cu and CNTs for 16nm technology. For analyzing peak overshoot, the interconnect lengths are varied from 100um to 500um in 16 technology node for Cu, single walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). The values of the peak overshoot and overshoot width changes, as the interconnect length increases, the peak overshoot and width is going to be increases. As Compared to Cu, SWCNT and MWCNT, the peak overshoot and width for SWCNT is lesser than copper and MWCNT. The MWCNT interconnect is less than that of conventional Copper interconnects.

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Section: Introductionmentioning

confidence: 99%

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

Venkataiah¹,

Setty²,

Ramanjaneyulu³

et al. 2023

International Journal of Emerging Research in Engineering, Science, and Management

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“…Inductive effect and capacitive coupling effect gives interconnect wire coupling crosstalk significant and cause many signal integrity problems. Hence, interconnect wire down scaling is thus careful to be the real contest to CMOS scaling [12][13][14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Analysis of On-chip VLSI Interconnects

Jayamma¹,

Ramanjaneyulu²,

Sathish³

et al. 2022

International Journal of Emerging Research in Engineering, Science, and Management

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In this paper dynamic crosstalk is analyzed for coupled on-chip VLSI interconnects in different conditions. The proposed work has taken the MOS transistor analytical expressions. In this work, calculated the transition delays and different timings of the interconnect aggressor and interconnect victim drivers for in-phase switching and out-of-phase switching. All the calculated results are compared with simulations in SPICE. The average error in the transmission delay using SPICE is 2.02 and 3.274% for the interconnect aggressor and interconnect victim buffers for in phase switching, respectively. The average errors in the same are 2.3 and 1.87% for out phase switching event.

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Global RC Interconnects with ADL Buffers for Low-Power Applications

Bhardwaj,

Jain,

Sohal

2024

MNS

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Introduction: Interconnects are an essential requirement for any circuit completion. They are utilised to connect two or more blocks, yet when creating a circuit, certain problems have been observed. Scaling back technology is one such problem. Methods: With technology scaled down their aspects change which can straightforwardly affect the circuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits has increased. Certain wire (RC) models and techniques have previously been characterized to control these performance parameters however in this paper, authors have proposed a new interconnect structure with a buffer insertion technique using adiabatic dynamic logic (ADL). Results: To optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect circuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the entire circuit. Conclusion: The suggested model's performance is compared to that of other cutting-edge methods. result: The complete circuits are modelled and simulated using the SPICE tool. A performance comparison is done between the existing model and the proposed model.

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Effect of Line Parasitic Variations on Delay and Energy of Global On-Chip VLSI Interconnects in DSM Technology

Cited by 3 publications

References 8 publications

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

Crosstalk Analysis of On-chip VLSI Interconnects

Global RC Interconnects with ADL Buffers for Low-Power Applications

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