Effect of Ion Flux in Source-Drain Extension Ion Implantation for 10-nm Node FinFet and beyond on 300/450mm Platforms

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

“…These devices, due to the addition of the polarity gate, allowed us to exploit the electrostatic doping of the source and drain Schottky junctions to dynamically set the polarity of the transistors at run time, removing the need for any physical or chemical doping. We tested individual transistors and demonstrated polarity-controllable behavior, achieving ON/OFF ratios >10 5 for both polarities on the same device with subthreshold swings as low as 80 mV/dec. The enhanced switching properties of the single devices allowed us to experimentally demonstrate highly compact and expressive XOR and MAJ gates, with fewer transistors than possible in a conventional CMOS logic.…”

“…With the physical gate length of modern devices approaching 10 nm, ion implantation has become increasingly more complicated to control. , Fluctuations in number of dopant atoms present in the transistor channel are responsible for an increased variability of the threshold voltage of the devices . In addition, ion implantation requires high-temperature annealing to repair damages in the silicon and achieve proper dopant activation. , This high-temperature process is not compatible with the process for monolithic 3D-CMOS, which requires a low thermal budget. A device concept that would not rely on any physical doping and use undoped materials would be of great interest in this regard.…”

“…4 In addition, ion implantation requires high-temperature annealing to repair damages in the silicon and achieve proper dopant activation. 5,6 This high-temperature process is not compatible with the process for monolithic 3D-CMOS, which requires a low thermal budget. A device concept that would not rely on any physical doping and use undoped materials would be of great interest in this regard.…”

FinFET Towards Nano-Transistor: A Review

“…The inversion layers' form at both sides of the channel so the device channel width can be approximated as twice of the fin height. The drive current of the FinFET can be easily multiplied by designing several fins in one FinFET device as in FIGURE 2 (b), [18]. Although the FinFET has more advantages in device performance than planar MOSFET, the momentum for FinFET development in academia did not pick up until early 2000, when the scaling of planar MOSFET was approaching its end.…”