Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

Maharrey, J. A.; Quinn, R. C.; Loveless, T. D.; Kauppila, J. S.; Jagannathan, S.; Atkinson, N. M.; Gaspard, N. J.; Zhang, E. X.; Alles, Michael L.; Bhuva, B. L.; Holman, W.T.; Massengill, L.W.

doi:10.1109/tns.2013.2288572

Cited by 22 publications

(6 citation statements)

References 13 publications

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“…Depending on different parameters such as particle energy and gate output load, SETs originating at the circuit gates will have different initial widths [21, 22]. Therefore in order to have a comprehensive analysis, the error probability should be obtained considering different possible values of SET initial widths.…”

Section: Resultsmentioning

confidence: 99%

“…The type of function f (w) depends on different factors such as the particles' energy and the critical charge for circuit transistors [20][21][22][23]. There have been several works that present different ways to determine f (w) [3,6,10].…”

Section: Ser Estimation Formulationmentioning

confidence: 99%

“…where t is the maximum possible width for SETs in a specific technology node [21,22]. Please note that W SET and t depends on different parameters especially the operating environment.…”

Section: Error Probability Computationmentioning

confidence: 99%

“…Considering the procedure described in Appendix 1, the probability of SE c can be calculated as

P false(normalS {normalE}_{normalc} false) = \frac{1}{N_{normalCNS}} {false\sum}_{i = 1}^{N_{CNS}} \int_{w_{normalmin}}^{w_{normalmax}} P (E_{i, w}) \cdot f (w) \cdot d w

where N CNS is the number of the circuit nodes (i.e. circuit gate outputs), ( w min and w max ) are the (minimum and maximum) width of SETs in the circuit nodes; E i , w as the event of any PO failing (experience a soft error) given that the SET occurs at the output of the CN i with the initial width of w and P ( E i , w ) is the probability of E i , w ; and f ( w ) is the probability density function of random variable

scriptW \in false(w_{truemin}, w_{truemax} false)

. The type of function f ( w ) depends on different factors such as the particles’ energy and the critical charge for circuit transistors [20–23]. There have been several works that present different ways to determine f ( w ) [3, 6, 10].…”

Section: Ser Estimation Formulationmentioning

confidence: 99%

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Soft error rate estimation of combinational circuits based on vulnerability analysis

Raji

Pedram

Ghavami³

2015

IET Computers & Digital Techniques

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Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backwardtraversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo-based fault injection simulation on ISCAS'85 benchmark circuits.

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Section: Resultsmentioning

confidence: 99%

Section: Ser Estimation Formulationmentioning

confidence: 99%

“…where t is the maximum possible width for SETs in a specific technology node [21,22]. Please note that W SET and t depends on different parameters especially the operating environment.…”

Section: Error Probability Computationmentioning

confidence: 99%

“…Considering the procedure described in Appendix 1, the probability of SE c can be calculated as

P false(normalS {normalE}_{normalc} false) = \frac{1}{N_{normalCNS}} {false\sum}_{i = 1}^{N_{CNS}} \int_{w_{normalmin}}^{w_{normalmax}} P (E_{i, w}) \cdot f (w) \cdot d w

scriptW \in false(w_{truemin}, w_{truemax} false)

Section: Ser Estimation Formulationmentioning

confidence: 99%

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Soft error rate estimation of combinational circuits based on vulnerability analysis

Raji

Pedram

Ghavami³

2015

IET Computers & Digital Techniques

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“…Thus the charge collection process dynamically interacts with and during the circuit response [71]. SETs with pulse width capable of propagating through integrated digital circuits are of the order of several tens of picoseconds for sub-32 nm FDSOI technologies [72].…”

Section: Set Propagation and Capture In Integrated Circuitsmentioning

confidence: 99%

Modeling Single Event Transients in Advanced Devices and ICs

Artola

Gaillardin

Hubert

et al. 2015

IEEE Trans. Nucl. Sci.

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The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the art of modeling at each scale, this paper will discuss current capabilities and intrinsic limitations of SET modeling, the incoming challenges in advanced devices and ICs, and finally the methodologies to improve SET simulation and prediction for future technologies.

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Soft Error Rate Estimation of VLSI Circuits

Ghavami

Raji

2020

Soft Error Reliability of VLSI Circuits

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Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

Cited by 22 publications

References 13 publications

Soft error rate estimation of combinational circuits based on vulnerability analysis

Soft error rate estimation of combinational circuits based on vulnerability analysis

Modeling Single Event Transients in Advanced Devices and ICs

Soft Error Rate Estimation of VLSI Circuits

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