Soft error rate estimation of combinational circuits based on vulnerability analysis

Raji, Mohsen; Pedram, Hossein; Ghavami, Behnam

doi:10.1049/iet-cdt.2014.0157

Cited by 11 publications

(8 citation statements)

References 29 publications

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“…A transmission-gate approach to filter out soft errors is proposed in [39] based on adjusting the gate and body bias voltages. A vulnerability analysis approach introduced in [31] is applied in order to consider the impacts of process variation in finding the most vulnerable circuit gates to soft error. The mentioned related works are suffering from a serious shortcoming.…”

Section: Previous Workmentioning

confidence: 99%

Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

2019

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Due to the reduction in device feature size and supply voltage, achieving soft error reliability in sub-micrometer digital circuits is becoming extremely challenging. We consider the problem of choosing the gate sizes in a combinational logic circuit in order to minimize the soft error rate (SER) of the circuit. This problem can be solved using the heuristic as well as the greedy-based approaches for small-size problems; however, when the circuit size increases, the computational time grows exponentially, and hence, the previous methods become impractical. This paper proposes a novel technique for soft error tolerant design of largescale combinational circuits using a cone-oriented gate sizing. Circuit partitioning is used to split the circuit into a set of small sub-circuits. The gates of sub-circuits are resized, such that the entire circuit SER is reduced based on a new soft error descriptor metric. The proposed cone-oriented gate sizing framework is used for selective gate sizing, leading up to 31% SER reduction with less than 17% area overhead when applied to large-scale benchmarks. The results also show that the proposed method is 21% more efficient and up to 292 times faster when compared with that obtained using a similar work based on the sensitive-based gate sizing scheme.

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Section: Previous Workmentioning

confidence: 99%

Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

2019

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“…This metric should be able to estimate the contribution of each cell to the total SER of the circuit. There are some SER metrics in the literature, but we choose PVW [4] [36], as its results are quite close to Monte Carlo results and its computation time is very low.…”

Section: A Quadratic Placement Formulationmentioning

confidence: 93%

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs

Kiarash¹,

Pedram²,

Ghavami³

et al. 2021

Preprint

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Nowadays nanoscale combinational circuits are facing significant reliability challenges including soft errors and process variations. This paper presents novel process variation-aware placement strategies that include two algorithms to increase the reliability of combinational circuits against both Single Event Transients (SETs) and Multiple Event Transients (METs). The first proposed algorithm is a global placement method (called SeaPlace-G) that places the cells for hardening the circuit against SETs by solving a quadratic formulation. Afterwards, a detailed placement algorithm (named SeaPlace-D) is proposed to increase the circuit reliability against METs by solving a linear programming optimization problem. Experimental results show that SeaPlace-G and SeaPlace-D averagely achieve 41.78% and 32.04% soft error reliability improvement against SET and MET, respectively. Moreover, when SeaPlace-D is followed by SeaPlace-G, MET reduction can be improved by up to 53.3%.

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“…dynamic and static. The dynamic SER method is used mostly with the fault injection techniques and logic simulation methodologies [12], [13]. To overwhelm the consequences of these errors in digital designs, many fault tolerance techniques have been presented in the last few decades.…”

Section: Related Workmentioning

confidence: 99%

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

Khatri¹

2020

IJACSA

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The FPGA has been involved in many safety and mission-critical applications in the last few decades. FPGA designs are also critical to errors and failures due to radiations. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. The primary objective of any fault tolerance technique is to produce a dependable system. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. Faulttolerant techniques can detect the faults and correct them, or mask the faults. The overview of the most standard techniques used for FPGA designs is described in the paper. Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The proposed TMR code generator for implementing the FPGA design is also described. These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.

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Soft error rate estimation of combinational circuits based on vulnerability analysis

Cited by 11 publications

References 29 publications

Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

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