Effect of Buffer Layer on Single-Event Burnout of Power DMOSFETs

Interpreting Space-Mission LET Requirements for SEGR in Power MOSFETs

“…The calibrated and predictive models developed in this study provide support for the Titus-Wheatley expression given in (1) in which the ion atomic number, as opposed to LET, is the important parameter for determining the electric field needed to rupture the oxide. Rupture occurs when the sum of the applied Vgs and the transient field generated by the epilayer response to an ion strike exceeds this critical field.…”

“…Two potentially catastrophic failure mechanisms create a radiation hardness assurance challenge for these devices when biased in the off-state: single-event gate rupture (SEGR) and single-event burnout (SEB). Over time, successful process-level methods for reducing SEB susceptibility have been implemented [1]- [4] elevating the profile of SEGR as a continued concern in radiation-hardened vertical power MOSFETs. In part due to the severity of SEGR consequences and in part due to the difficulty of accurate SEGR rate estimation, SEGR mitigation methodologies emphasize risk avoidance, using heavy-ion accelerator tests to define safe operating conditions for a surface-incident linear energy transfer (LET).…”

Temperature dependence of single-event burnout for super junction MOSFET

“…It is known that the additional dr the SEB tolerance [2,4]. As shown that the additional drain buffer laye tolerance at low temperature.…”

“…Many studies on SEB of MOSFET by cosmic ray have been presented. Generally, the SEB failure mechanism for MOSFET is explained as follows: electron and hole pairs are generated by a cosmic ray particle, then the holes flow into source n+ as a base current of parasitic npn transistor and electrons flow into n-epi layer as a collector current of the parasitic transistor, and the electrons enhance the electric field at the n-epi / n+ substrate interface and impact ionization increases in this region [3,4]. It is also reported that the tolerance of SEB increases when the temperature increases [5,6], but few papers attempt to explain the mechanism of this dependence of SEB tolerance on temperature.…”

Single-Event Burnout Hardened Structure of Power UMOSFETs With Schottky Source

“…Huang and Amaratunga have showed the analysis of SEB and single-event gate rupture (SEGR) in super-junction MOSFETs which can make the SEB and SEGR less sensitive [9]. It has also been found that the Manuscript addition of a buffer layer can improve the device's SEB threshold voltage, thus, improve the device's SEB performance [10]. Many researchers have attempted to discuss the SEB characterization in power MOSFETs with a buffer layer [11], [12].…”