2014
DOI: 10.1186/1556-276x-9-517
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Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

Abstract: This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresp… Show more

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Cited by 22 publications
(56 citation statements)
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“…A 46 nm ZnO layer was subsequently deposited at 190°C (Fig. 1c) by an Oxford Instrument Plasma Technology (OIPT) FlexAl Atomic Layer Deposition (ALD) system using diethyl zinc (DEZ) precursor (dose time of 50 milliseconds, pressure of 80 mTorr) and oxygen plasma (O 2 flow of 60 sccm, pressure of 15 mTorr and RF power of 100 W) [12]. Subsequently, a spacer etch was done to fully remove the ZnO layer leaving ZnO nanowires along the Si 3 N 4 step sidewalls (Fig.…”
Section: Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…A 46 nm ZnO layer was subsequently deposited at 190°C (Fig. 1c) by an Oxford Instrument Plasma Technology (OIPT) FlexAl Atomic Layer Deposition (ALD) system using diethyl zinc (DEZ) precursor (dose time of 50 milliseconds, pressure of 80 mTorr) and oxygen plasma (O 2 flow of 60 sccm, pressure of 15 mTorr and RF power of 100 W) [12]. Subsequently, a spacer etch was done to fully remove the ZnO layer leaving ZnO nanowires along the Si 3 N 4 step sidewalls (Fig.…”
Section: Methodsmentioning
confidence: 99%
“…Recently, top-down ZnO nanowires were reported to be fabricated using conventional lithography, atomic layer deposition (ALD) and RIE [11]. However, the transistors of [12] were formed at chip level and cannot be directly transferred to wafer level due to issues such as chemical loading effects and plasma condition changes. The plasma-based chemical etch processes normally require complicated optimizations and are not transferable to other materials and wafer-size changes.…”
Section: Introductionmentioning
confidence: 99%
“…The device has two nanowires in parallel The electrical I-V characterization of the ZnO NWFETs was performed using an Agilent Technologies B1500A semiconductor parametric analyser. Hall measurements were made on the ZnO layer and the results were compared with results reported by other researchers [4,[6][7][8][9][10][11][12][13][14].…”
Section: Device Fabricationmentioning
confidence: 99%
“…This work aims to improve an existing process developed by S. M. Sultan et al, [6] on the remote plasma atomic layer deposition (RPALD) process. All other steps were kept relatively the same.…”
Section: Process Optimisationmentioning
confidence: 99%
“…Previous top-down ZnO n based on low cost photolithography, conf and anisotropic etching method. It ha fabrication control of the dimension and wafer [11]. The pre-determined orientation the substrate enable the nanowires to be functional sensing device.…”
mentioning
confidence: 99%