Effect of ALD- and PEALD- Grown Al2O3 Gate Insulators on Electrical and Stability Properties for a-IGZO Thin-Film Transistor

Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator

“…Shown in Figure a,b are the schematic diagram and SEM image of SATG a-IGZO TFT with 4-nm AlO x GI, where the channel width ( W ) and length ( L ) are 20 and 9 μm, respectively. In the TG architecture, the ALD process of high- k dielectrics is conducted after the deposition of the AOS channel, which would increase the risk of incidental damages to AOS , and channel/GI interface. − Figure c shows the HRTEM images of the a-IGZO/AlO x interface in the channel region of the SATG TFT. The AlO x GI layer has a physical thickness of 4.0 nm, and its interfaces with the a-IGZO channel and Mo TG are both fairly clear, which is consistent with the smooth surfaces of sputtered a-IGZO and ALD AlO x as observed by AFM (Figure ).…”

“…However, the self-aligned top-gate (SATG) AOS TFT with smaller parasitic capacitance and better scalability , is preferred by the advanced applications, wherein the post-AOS GI deposition places a daunting challenge on realizing ultrathin top-gate (TG) EOT with ALD high- k dielectrics. The associated ALD processes with chemically reactive species often induced abundant defect states at the GI/channel interface − and in the AOS channel. , These defect states can result in the increased off-state current ( I off ), a reduced on/off ratio, poor subthreshold swing (SS), and a negative threshold voltage ( V th ) shift, , while the defect-sensitive stabilities could deteriorate even more severely. , Therefore, it is highly desired to clarify the interaction mechanism between the top AlO x GI and the bottom a-IGZO channel, in order to direct the suppression of defect generation during the ALD process and thus enable the high performance and reliability of ultrathin-EOT SATG AOS TFTs.…”

Amorphous InGaZnO (a-IGZO) Synaptic Transistor for Neuromorphic Computing

“…Interfacial trap density is also important because charge trapping/detrapping causes clockwise transfer curve hysteresis, which impedes the effect of EDL. The mobile ions can be neutralized by the interfacial traps, and electrons in the channel are repelled by the trapped electrons. ,, The concentration of hydrogen atoms and interfacial traps of ALD- and PEALD-Al 2 O 3 are affected by the oxidants and plasma time . Additionally, the deposition temperature should be chosen carefully since the surface roughness of thin film that varies with the thermal energy influences the interfacial traps .…”

“…104,108,109 The concentration of hydrogen atoms and interfacial traps of ALD-and PEALD-Al 2 O 3 are affected by the oxidants and plasma time. 110 Additionally, the deposition temperature should be chosen carefully since the surface roughness of thin film that varies with the thermal energy influences the interfacial traps. 111 It was reported that plasma treatment can effectively reduce these interfacial traps.…”

High-Performance Self-Aligned Top-Gate Amorphous InGaZnO TFTs With 4 nm-Thick Atomic-Layer-Deposited AlOx Insulator

“…Therefore, it is highly desired to develop ultrathin-GI SATG TFTs with wellmaintained superiorities. Compared to the GI deposition in BG architectures, the growth of high-k GI is much more challenging in top-gate AOS TFTs, since it would possibly damage the predeposited AOS channel [23].…”