Editors' Choice—Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures

Abstract

Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET and Gate All Around devices. We use Si 4 H 10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 • C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.

Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices

“…In the case of Ge pMOS, compressive Ge channels are grown on top of a Ge‐rich Si 1− y Ge y SRB (e.g., y = 0.7), which allows for enhanced channel carriers mobilities and improved electrostatics . Ge:B and Ge 1− z Sn z :B ( z ≈ 1–2%) are then preferred as S/D materials due to process compatibility (limited thermal budget) and appropriate strain . In this contribution, we elaborate on the low‐temperature epitaxial growth of heavily doped Ge:B with the cyclic deposition‐etch (CDE) method introduced elsewhere .…”

Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

“…6 Si passivation for Ge-rich channels.-The epitaxial growth of ultra-thin Si layers on (strained) Ge fins or nanowires has been thoroughly discussed in Ref. 18. In this work, Si 3 H 8 and Si 4 H 10 were used as Si precursors to enable the epitaxy of very thin Si films to passivate Ge channels at temperatures as low as 330°C.…”

Scavenging Segregated Ge on Thin Single-Crystal Si Epitaxially Grown on Ge

“…To minimize the Ge segregation (segGe) and the GeO x formation in the gate dielectrics, a Si layer on Ge using chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) was employed. Compared with the approaches of oxidized Ge and high-κ deposition on Ge, where the formation of GeO x is inevitable, the diffusion of Ge (diff-Ge) into the thin Si layer and segGe on top of the Si surface lessened in the Si-layer approaches, although it still occurred; these were studied by synchrotron radiation photoelectron spectroscopy (SRPES) for the MBE epi -Si/Ge and by secondary-ion mass spectroscopy (SIMS) for the CVD Si/Ge. , A thick Si layer may reduce the segGe but degrades the electron mobility of the devices . In comparison, thin Si of a few monolayers (MLs) produces a smaller conduction band offset between Ge and Si, allowing more electrons to distribute in the Ge channel with higher electron mobility, but causing more segGe in the meantime .…”

“…Therefore, it is a challenge to further reduce or completely remove the segGe and the GeO x formation in the gate dielectrics to attain reliable n-Ge MOS for the epi -Si/Ge or the Si-cap/Si approaches. , In this work, we have used sequential room-temperature oxidation followed by thermal annealing in ultra-high vacuum (UHV), called a scavenging process, in removing the diff-Ge in the thin epi- Si and reducing the segGe on the top epi -Si/Ge surface. A repeat of the scavenging process has further reduced the residual segGe and Si surface atoms, produced more Si 4+ oxidation states, and formed epi -Si/Ge free of GeO x .…”