Si1–x Ge x with Ge contents higher than x = 0.5 is expected to boost on-current and improve reliability of p-channel metal-oxide-semiconductor (pMOS) devices. However, unavoidable GeO x formation at the high-κ/Si1‑x Ge x interface with high Ge-contents (HGC) has caused high interfacial trap density, posing a challenge for employing the HGC Si1‑x Ge x as the channel in sub-3 nm complementary MOS technology. In this work, we have deposited epitaxial Si (epi-Si) of six monolayer thickness on Si1–x Ge x at temperatures of 260–280 °C to minimize Ge diffusion and segregation. Si1–x Ge x layers with a wide range of HGC (0.5 < x ≤ 0.8) were grown to investigate the effectiveness of the epi-Si on the Si1–x Ge x . To minimize the GeO x formation caused by the oxidation of the segregated Ge on the epi-Si surface, HfO2 was subsequently deposited via e-beam evaporation on the epi-Si. The measurements using reflection high-energy electron diffraction, high-resolution synchrotron radiation X-ray diffraction, and scanning transmission electron microscopy with high-angle annular-dark-field imaging have revealed the high crystallinity of the epi-Si, the Si1–x Ge x layers, and abrupt interfaces of the high-κ/epi-Si/Si1–x Ge x layers. The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit ) of (3–6) × 1011 eV–1 cm–2 in these high-κ/epi-Si/(HGC)Si1–x Ge x samples. The minimum Dit values remained at 3 × 1011 eV–1 cm–2 regardless of the Ge content, confirming the effective passivation of the low-temperature deposited epi-Si. By extracting the effective charge sheet densities for the Si1–x Ge x gate stacks via examination of capacitance–voltage (C–V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors, we have attained very high acceleration factors of 8–12, indicating high reliability of the HfO2/epi-Si/SiGe pMOS gate stacks.
Single-crystal Si with six monolayers in thickness was epitaxially grown on epi-Ge(001). The Si surface is characterized with the Ge atoms segregated from the underlying epi-Ge. Some of the Ge atoms bond with the Si inside the film. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in situ annealing at 500 °C under ultra-high vacuum moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeO x , but with a very small amount of segregated Ge. Using the scavenging process in reducing the segregated Ge prior to the high-κ deposition, the C–V hysteresis of the high-κ/epi-Si/n-Ge(001) metal-oxide-semiconductor (MOS) capacitors decreased more than two times, meaning that the electron traps contributed from the GeO x in the high-κ/epi-Si/Ge(001) are reduced.
Single-crystal Si films six-monolayers (MLs) in thickness were epitaxially grown on Ge(001) surface to minimize the formation of undesirable GeOx with subsequent deposition of HfO2 and Y2O3. The interfacial properties and reliability of the in-situ deposited high-κ oxides on epi-Si/p-Ge(001) were compared. We have achieved interface trap density (Dit ) values of (1- 3) × 1011 eV-1 cm-2 in the Y2O3/epi-Si/p-Ge, which are two times lower than those of the HfO2/epi-Si/p-Ge(001). The capacitance-equivalent-thicknesses (CET) under different annealing conditions were extracted to analyze the interdiffusion in the gate stacks under various thermal treatments. Y2O3/epi-Si/p-Ge exhibited higher thermal stability than HfO2. In both high-κ’s gate stacks, the effective charge sheet densities (∆Neff ) are lower than the targeted value of 3 × 1010 cm-2. Compared to the Y2O3 gate stacks, attainment of a high acceleration factor of 11 in the HfO2/epi-Si/p-Ge gate stacks suggested an improved defect-carrier decoupling in the latter stacks.
Si capping layer is the most notable approach used in Ge metal-oxide-semiconductor (MOS);1-2 however, the Ge segregation and diffusion occurred during the growth of Si.3-4 The formation of undesirable GeOx is detrimental to the Ge nMOS reliability.5 This work focuses on using the scavenging process to reduce the segregated Ge atoms and to completely remove GeOx in the high-k/epi-Si/epi-Ge(001). We used high-resolution synchrotron radiation photoelectron spectroscopy (SRPES) to show the detailed development of Ge segregation and scavenging Ge using in-situ film growth, oxidation, and annealing. The Si films in 8Å thickness were grown on the epi-Ge(001) in a semiconductor molecular beam epitaxy (MBE) chamber.2 These samples were in-situ transferred to National Synchrotron Radiation Research Center in Taiwan for electronic structure studies using photoemission. Molecular oxygen was exposed to the epi-Si/epi-Ge(001) surfaces at 300°C in the photoemission chamber. The samples were then in-situ annealed at 500°C for 5 min under an ultra-high vacuum (UHV). The topmost surface of epi-Ge(001) is terminated with Ge-Ge buckled dimers.6 In the case of room-temperature grown amorphous Si (a-Si) film, the intensity of the Ge down-dimer component from the underlying epi-Ge remains as it is. The Ge up-dimer atoms were partly diffused into the a-Si film, and some of them were segregated to the top of the a-Si surface. The epi-Si grown at 260 - 280°C causes the rest of the Ge down-dimer atoms to move to the epi-Si surface to become both segregated Ge (segGe) and diffused Ge (diff-Ge). The growth of Si merely affects the topmost surface, and the Ge atoms in the second layer of the epi-Ge remain intact. A comparison of the amount of GeOx for HfO2/epi-Si/epi-Ge(001) and HfO2/epi-Ge(001) shows that the epi-Si has greatly reduced the amount of GeOx. However, the GeOx, segGe and diff-Ge components are still observed in the HfO2/epi-Si/Ge(001) samples. We have previously reported that three-time scavenging cycles have greatly reduced the amount of segGe and diff-Ge atoms in high-κ/epi-Si/n-Ge(001), thus decreasing electron traps.7 Each scavenging cycle includes room-temperature oxidation followed by thermal annealing. In this study, the oxidation of the as-grown epi-Si/epi-Ge(001) samples was performed at 300°C. It is worth noting that there is no GeOx formation on the surface after the thermal oxidation, which is different from the room-temperature oxidation of the epi-Si/epi-Ge(001) surfaces. In addition, the oxidation at 300°C affects part of the diff-Ge atoms to evaporate from the surface, which is also different from our previous work, where the diff-Ge component shows no change in intensity since the oxidation occurred at room temperature. The subsequent in-situ annealing at 500°C moved the residual Ge-boned Si (diff-Ge) inside the epi-Si to the surface to become part of the segGe atoms. In conclusion, we have used the aforementioned process to further reduce the segregated Ge, and thus the GeOx, on top of the epi-Si/epi-Ge(001). To whom the correspondence is addressed: mhong@phys.ntu.edu.tw (M. Hong), raynien@phys.nthu.edu.tw (J. Kwo), and pi@nsrrc.org.tw (T. W. Pi) Acknowledgments This work is supported by MOST 110-2112-M-002-036-, 110-2622-8-002-014-, 110-2923-M-002-001-, and 110-2112-M-213-012- of the Ministry of Science and Technology in Taiwan. Reference 1 H. Arimura, E. Capogreco, A. Vohra, C. Porret, R. Loo, E. Rosseel, A. Hikavyy, D. Cott, G. Boccardi, L. Witters, G. Eneman, J. Mitard, N. Collaert, and N. Horiguchi, IEEE Int. Electron Devices Meet., 2.1.1−2.1.4 (2020). 2 H. W. Wan, Y. J. Hong, Y. T. Cheng, C. K. Cheng, C. H. Hsu, C. T. Wu, T. W. Pi, J. Kwo, and M. Hong, M., ACS Appl. Electron. Mater. 3, 2164−2169 (2021). 3 R. Loo, H. Arimura, D. Cott, L. Witters, G. Pourtois, A. Schulze, B. Douhard, W. Vanherle, G. Eneman, O. Richard, P. Favia, J. Mitard, D. Mocuta, R. Langer, N. Collaert, ECS J. Solid State Sci. Technol. 7, 66−72 (2018). 4 Y. T. Cheng, H. W. Wan, C. K. Cheng, C. P. Cheng, J. Kwo, M. Hong, T. W. Pi, Appl. Phys. Express 13, 085504 (2020). 5 J. Franco, B. Kaczer, P. J. Roussel, J. Mitard, S. Sioncke, L. Witters, H. Mertens, T. Grasser, G. Groeseneken, IEEE Int. Electron Devices Meet., 15.2.1−15.2.4 (2013). 6 Y. T. Cheng, Y. H. Lin, W. S. Chen, K. Y. Lin, H. W. Wan, C. P. Cheng, H. H. Cheng, J. Kwo, M. Hong, T. W. Pi, Appl. Phys. Express 10, 075701 (2017). 7 Y. T. Cheng, H. W. Wan, T. Y. Chu, T. W. Pi, J. Kwo, M. Hong, ACS Appl. Electron. Mater. 3, 4484-4489 (2021).
Silicon-germanium (SiGe) is replacing silicon (Si) as the channel layer for the p-type metal-oxide-semiconductor (pMOS) in the aggressively scaled complementary MOS (CMOS) technology. Many research efforts involving SiGe gate stacks have resulted in the attainment of low interfacial trap densities (Dits). Si-passivated SiGe gate stacks are the most promising method to achieve both low Dit and high device reliability. However, regardless of the growth methods, most publications reported the pileup of Ge atoms on top of the grown Si even after extensive treatments. The subsequent process in forming gate stacks, including oxidation, inevitably caused the segregated Ge to form GeOx, leading to degradation of the interfacial quality of the gate stacks. We have used molecular beam epitaxy (MBE) to grow thin single-crystal Si of 0.79nm thickness (six MLs) epitaxially on epi-Si1-xGex(001) under ultra-high vacuum (UHV). Different from its counterpart of chemical vapor deposition (CVD), MBE enables epi-Si growth on Ge at growth temperatures below 300 °C. The measurements using reflection high-energy electron diffraction (RHEED), high-resolution synchrotron radiation X-ray diffraction (HR-XRD), and the scanning transmission electron microscopy with high-angle annular-dark-field (STEM-HAADF) have revealed high crystallinity of the epi-Si, the Si1-xGex layers and abrupt interfaces of the high-k/epi-Si/Si1-xGex layers. Moreover, our unique capability of epi growth/analysis enabled the study of the electronic surface structures of epi-Si/epi-Ge using in-situ high-resolution synchrotron radiation photoemission spectroscopy (SRPES) via a portable sample transfer station under UHV. We have used SRPES to demonstrate that the as-grown Si1−xGex(001)-2×1 surfaces with Ge content ranging from 0.1 to 0.9 are all terminated with buckled Ge–Ge dimers, and the surface electronic structure is similar to that of epi-Ge(001)-2×1. The direct deposition of epi-Si on as-grown SiGe removed the top buckled Ge-Ge dimers, which diffused into the epi-Si and some segregated to the top of the Si. As a result, the topmost layer beneath the epi-Si was 1 ML of Ge, and the interfaces of high-k/epi-Si/Si1−xGex are similar to those of the high-k/epi-Si/Ge. Again, the hetero-interfaces of our gate dielectrics are different from those grown using CVD. The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit) of (3 - 6) × 1011 eV-1cm-2 in these high-k/epi-Si/Si1-xGex samples. The minimum Dit values remained at 3 × 1011 eV-1cm-2 regardless of the Ge content, demonstrating the effective passivation of the low-temperature deposited epi-Si. The limited Ge segregation during the low-temperature growth of epi-Si may attribute to the attainment of the low Dit values. We have benchmarked the minimum Dit (Dit, min) of our work with other state-of-the-art SiGe gate stacks. The Dit,min values from the other efforts increased with increasing Ge content, which may be caused by the GeOx formation that was difficult to control in the high-Ge-content (HGC) Si1-xGex. The effective charge sheet densities for the Si1-xGex gate stacks were extracted via examination of capacitance-voltage (C-V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors. We have attained very high acceleration factors of 8-12, indicating high reliability of the HfO2/epi-Si/Si1-xGex pMOS gate stacks. Furthermore, we have used a scavenging method, consisting of a cyclic process of an O2 exposure followed by a UHV annealing, to eliminate the segregated and diffused Ge in epi-Si before high-k deposition. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in-situ annealing at 500 °C under UHV moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeOx, but with a minimal amount of segregated Ge.
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