With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

The key steps of a transfer of two-dimensional (2D) materials are the delamination of the as-grown material from a growth substrate and the lamination of the 2D material on a target substrate. In state-of-the-art transfer experiments, these steps remain very challenging, and transfer variations often result in unreliable 2D material properties. Here, it is demonstrated that interfacial water can insert between graphene and its growth substrate despite the hydrophobic behavior of graphene. It is understood that interfacial water is essential for an electrochemistry-based graphene delamination from a Pt surface. Additionally, the lamination of graphene to a target wafer is hindered by intercalation effects, which can even result in graphene delamination from the target wafer. For circumvention of these issues, a direct, support-free graphene transfer process is demonstrated, which relies on the formation of interfacial water between graphene and its growth surface, while avoiding water intercalation between graphene and the target wafer by using hydrophobic silane layers on the target wafer. The proposed direct graphene transfer also avoids polymer contamination (no temporary support layer) and eliminates the need for etching of the catalyst metal. Therefore, recycling of the growth template becomes feasible. The proposed transfer process might even open the door for the suggested atomic-scale interlocking-toy-brick-based stacking of different 2D materials, which will enable a more reliable fabrication of van der Waals heterostructure-based devices and applications.

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A Cl 2 etch of different group IV materials in a low temperature range (260-600 °C) is presented. It is shown that in general the Cl 2 etching behavior is very similar to that of HCl: Si is etched slowest, Ge fastest with SiGe being between these two cases. Activation energies for Cl 2 etching of Si, SiGe and Ge are very low and show that neither Cl nor H surface passivation are limiting factors for the etch. The etching rate is strongly affected by the choice of the carrier gas (He, H 2 and N 2 ) and by the process pressure which gives high flexibility for its application. As compared to HCl, Cl 2 allows decreasing of the etching process temperatures down to ∼400 °C for Si and ∼250 °C for Ge. Although it is not clear if co-flow selective processes are visible due to possible exothermic chain reaction of radicals in the presence of group IV hydrides, cyclic approaches can be relatively easily achieved at temperatures below 500 °C.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.