Early-life-failure detection using SAT-based ATPG

Sauer, Matthias; Kim, Young Moon; Seomun, Jun; Kim, Hyung-Ock; Do, Kyung-Tae; Choi, Jong Seob; Kim, Kee Sup; Mitra, Subhasish; Becker, Bernd

doi:10.1109/test.2013.6651925

Cited by 18 publications

(3 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The NSF Variability Expedition ( Figure 5) [49] seeks to build opportunistic computing systems where hardware variations are monitored and exposed to software layers (instead of being hidden behind pessimistic margins) enabling adaptations. The work has spanned circuit-level monitoring and test (e.g., [50], [51], [60]), variability emulation ( [52], [53]), runtime for embedded systems (e.g., [54], [55]), GPUs (e.g., [56], [48]), processors (e.g., [56], [58]), memories (e.g., [55], [64], [59]) and storage (e.g., [61], [62]). In the following, we briefly describe some of the research on memory variability done under the Variability Expedition.…”

Section: Variability Expeditionmentioning

confidence: 99%

Multi-Layer Memory Resiliency

Dutt

Gupta

Nicolau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

View full text Add to dashboard Cite

With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications. Memories are susceptible to degradation and failures from a wide range of manufacturing, operational and environmental effects, requiring a multi-layer hardware/software approach that can tolerate, adapt and even opportunistically exploit such effects. The overall memory hierarchy is also highly vulnerable to the adverse effects of variability and operational stress. After reviewing the major memory degradation and failure modes, this paper describes the challenges for dependability across the memory hierarchy, and outlines research efforts to achieve multi-layer memory resilience using a hardware/software approach. Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with disabling faulty blocks; and second we show how software characteristics can be exposed to the architecture in order to mitigate the aging of large register files in GPGPUs. These approaches can further benefit from semantic retention of application intent to enhance memory dependability across multiple abstraction levels, including applications, compilers, run-time systems, and hardware platforms.

show abstract

Section: Variability Expeditionmentioning

confidence: 99%

Multi-Layer Memory Resiliency

Dutt

Gupta

Nicolau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…SDDs need to be detected to improve the overall quality of the product. The main problem with Small Delay Faults is that it is not always possible to detect them with at-speed tests; in fact, some SDFs show resistance against state-of-the-art timing-aware tests [4][5][6]. Since, they can only be propagated over paths with very large slacks, such faults are also called Hidden Delay Faults (HDFs) and pose a reliability issue, as they can cause an early life failure of the device [7].…”

Section: Introductionmentioning

confidence: 99%

X-Sand Filter: An X-Tolerant Response Compaction Technique for Faster-Than-At-Speed Testing

Ahmad

Iqbal

2020

Mehran Univ. res. j. eng. technol.

View full text Add to dashboard Cite

Faster-than-at-speed testing provides an effective way of detecting small delay defects but at the cost of increased number of unknown logic values on longer paths of the circuit under test. For efficient testing, these unknown logic values need to be filtered out of the circuit under test output. In past, different compaction hardware schemes were presented to minimize these unknown logic values, all these schemes were effective in handling a limited number of unknown values arising due to design imperfections, processing problems manufacturing problems material problems etc. but no effective compaction scheme is available to handle large number of these logic values arising due to faster-than-at-speed testing. This paper presents “X-sand filter”, a compaction technique, an extension of already presented idea of “X-tolerant signature analysis”. Here, the idea of “X-tolerant signature analysis” with modifications has been applied and has attained a considerable improvement in the X-tolerance. X-sand filter is a hierarchical structure that handles gradual X-density reduction in an efficient manner. Simulation results obtained show that we can achieve up to 90 % reduction in the X-density if we use X-sand filter. Extensions to the work of X-sand filter can be carried out in future to enhance its capabilities and make its configuration more flexible in terms of layer designing.

show abstract

“…Therefore, timing-aware Automatic Test Pattern Generation (ATPG) tries to identify long propagation paths with little slack. 6,7 But some SDFs cannot be propagated over long paths, and thus cannot be detected using the nominal clock frequency f nom . To make these Hidden Delay Faults (HDFs) detectable, the slack has to be reduced.…”

Section: Introductionmentioning

confidence: 99%

Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test

Sprenger

Hellebrand

2019

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([Formula: see text]-values). These [Formula: see text]-values impede the test response compaction. In addition, the number and distribution of the [Formula: see text]-values vary with the clock frequency, and thus a very flexible [Formula: see text]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [Formula: see text]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [Formula: see text]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [Formula: see text]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [Formula: see text]-reduction and fault efficiency can be adapted to user-defined goals.

show abstract

Early-life-failure detection using SAT-based ATPG

Cited by 18 publications

References 38 publications

Multi-Layer Memory Resiliency

Multi-Layer Memory Resiliency

X-Sand Filter: An X-Tolerant Response Compaction Technique for Faster-Than-At-Speed Testing

Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test

Contact Info

Product

Resources

About