Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Tasdizen, Ozgur; Akın, Abdulkadir; Kükner, Halil; Hamzaoğlu, İlker

doi:10.1109/tce.2009.5278038

Cited by 27 publications

(20 citation statements)

References 20 publications

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“…Table 2 also presents comparisons with related works. This work was compared with the works [6], [8], [10], [11], [12], [13] and [14], presented in section 2. Table 2 presents the following parameters: (1) the technology, (2) the maximum operation frequency reached, (3) consumed area, (4) used memory bits, (5) cycles used per block, (6) reached frames per second for Full HD videos, (7) reached frames per second for QFHDvideo and (8) the power consumption.…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…Comparing with [10], our architecture uses a lower number of clock cycles to process one block and it achieves a better operational frequency, allowing S&IS architecture to reacha better processing rate. On other hand, [10] uses a lower area and also a lower number of memory bits.…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…On other hand, [10] uses a lower area and also a lower number of memory bits. The work [10] is only capable to process Full HDvideos in real time at 34 frames per second, while our architecture could process 37.3 QFHD frames per second.…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…Step Search (DVSS) is proposed in [10] and it is capable to process 34.3 Full HDframes per second at 130 MHz. For low resolution videos, this algorithm achieves almost the same quality than FS, however, quality results for Full HD videos area not presented.…”

Section: Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design

Sanchez

Agostini

Sampaio

et al. 2012

2012 IEEE International Conference on Multimedia and Expo

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This paper presents the Spread and Iterative Search (S&IS) motion estimation algorithm, which uses a random spread evaluation together with a central iterative evaluation to avoid local minima falls and to increase the image quality for high definition videos. Considering Full HD videos, S&IS reached an average PSNR gain of 1.41dB when compared to Diamond Search (DS), with an increase of about four times in the number of evaluated blocks. When compared to Full Search (FS), the S&IS achieved an average PSNR loss of 1.56 dB, evaluating 73 times less blocks than FS. An efficient architecture for the S&IS algorithm is also presented in this paper.The architecture was designed targeting in real time processing (30 frames per seconds) for QFHD videos (3840×2160 pixels). The architecture was described in VHDL and synthesized for and Altera Stratix 4 FPGA and for ST90nm standard cells technology. Booth syntheses show that the architecture is able to process QFHD frames in real time. The standard cells version is able to reach also a good trade-off among area, memory and power consumption, processing QFHD videos with 62.2 mW.

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Section: Results and Comparisonsmentioning

confidence: 99%

Section: Results and Comparisonsmentioning

confidence: 99%

Section: Results and Comparisonsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design

Sanchez

Agostini

Sampaio

et al. 2012

2012 IEEE International Conference on Multimedia and Expo

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“…The concept was briefly introduced in [7] and it is further enhanced in this work to introduce a new instruction and to improve the utilization of Processing Element Groups (PEGs). Especially, the proposed MESIP is well suited to the fast search algorithms which have coarse search points in a large search area and different granularity search steps, such as diamond search (DS) [12], unsymmetrical-cross multi-hexagon-grid search (UMHS) [13] and dynamically variable step search (DVSS) [14], The proposed MESIP can handle real-time processing for various video sizes including high definition (HD) video and can efficiently support various ME algorithms. This paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Flexible IME instruction and its architecture for various fast ME algorithms

Kim

Bang²,

Sunwoo

2012

2012 IEEE International Symposium on Circuits and Systems

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This paper proposes Integer-pel Motion Estimation (IME) specific instructions and their hardware architecture for Motion Estimation Specific Instruction-set Processor (MESIP). With pattern information using the pixel distance, the proposed IME instruction efficiently supports fast search algorithms. The proposed MESIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The gate count is about 25.5K gates for each Processing Element Group (PEG) which has 128 SAD PEs. The total hardware size is about 453K gates and the operating frequency is 188MHz for 1080p@30frames in real time. MESIP can reduce the hardware size about 26% and the number of operation cycles about 18% compared with the prior version of MESIP and comparable to the existing ASICs.

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Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos

Sanchez

Corrêa

Noble

et al. 2012

Analog Integr Circ Sig Process

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Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Cited by 27 publications

References 20 publications

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design

Flexible IME instruction and its architecture for various fast ME algorithms

Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos

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