Flexible IME instruction and its architecture for various fast ME algorithms

Abstract

This paper proposes Integer-pel Motion Estimation (IME) specific instructions and their hardware architecture for Motion Estimation Specific Instruction-set Processor (MESIP). With pattern information using the pixel distance, the proposed IME instruction efficiently supports fast search algorithms. The proposed MESIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The gate count is about 25.5K gates for each Processing Element Group (PEG) which has 128 SAD PEs. The total hardware size is about 453K gates and the operating frequency is 188MHz for 1080p@30frames in real time. MESIP can reduce the hardware size about 26% and the number of operation cycles about 18% compared with the prior version of MESIP and comparable to the existing ASICs.