Dynamically reconfigurable FIR filter architectures with fast reconfiguration

Kumm, Martin; Möller, Konrad; Zipf, Peter

doi:10.1109/recosoc.2013.6581517

Cited by 22 publications

(10 citation statements)

References 20 publications

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“…A technique called Distributed Arithmetic, which predates FPGA [16], can be considered a generalization of the KCM technique to the MCM problem. From the abstract of [17] that, among other things, compares these two approaches, "if the input word size is greater than approximately half the number of coefficients, the LUT based multiplication scheme needs less resources than the DA architecture and vice versa". Such a rule of thumb (which of course depends on the coefficients themselves) should be reassessed with architectures computing just right on each side.…”

Section: Resultsmentioning

confidence: 99%

Sum-of-product architectures computing just right

Dinechin

Istoan

Massouri

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-Many digital filters and signal-processing transforms can be expressed as a sum of products with constants (SPC). This paper addresses the automatic construction of low-precision, but high accuracy SPC architectures: these architectures are specified as last-bit accurate with respect to a mathematical definition. In other words, they behave as if the computation was performed with infinite accuracy, then rounded only once to the low-precision output format. This eases the task of porting double-precision code (e.g. Matlab) to low-precision hardware or FPGA. The paper further discusses the construction of the most efficient architectures obeying such a specification, introducing several architectural improvements to this purpose. This approach is demonstrated in a generic, open-source architecture generator tool built upon the FloPoCo framework. It is evaluated on Finite Impulse Response filters for the ZigBee protocol.

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Section: Resultsmentioning

confidence: 99%

Sum-of-product architectures computing just right

Dinechin

Istoan

Massouri

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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“…However, as noted earlier, ASICs do not provide high flexibility in terms of reconfigurability [161]. FPGAs on the other hand are inherently built such that they support highly parallel algorithms and provide a higher degree of flexibility in terms of reconfiguration.…”

Section: Fpgas For Dsp Implementationmentioning

confidence: 99%

“…It allows for a high throughput even at low MHz clock rates. This has given birth to a new type of processing called reconfigurable processing, where FPGAs perform time intensive tasks instead of software [161,166,189,190].…”

Section: E Reconfigurable Dsp Implementation On Fpgamentioning

confidence: 99%

“…For applications like multi-stage filters for decimation and interpolation, polyphase FIR filters [193] or frequency variable filters for telecommunications and digital audio [194], multiplications with constants need to reconfigured from time to time [161].…”

Section: E Reconfigurable Dsp Implementation On Fpgamentioning

confidence: 99%

“…To change the logic only without reconfiguring the routing, for example changing the FIR filter coefficients, Xilinx FPGAs provide configurable LUT (CFGLUT). These LUTs can be reconfigured in 32 clock cycles by sourcing their contents from block RAM resources resulting in reconfiguration times of the order of 100 ns as compared to the ICAP interface where times are in order of microseconds to milliseconds [161]. These LUTs are similar to standard LUTs but provide a reconfiguration interface of data in, data out, clock enable and clock.…”

Section: E Reconfigurable Dsp Implementation On Fpgamentioning

confidence: 99%

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Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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Design Automation and Case Studies

Palchaudhuri

Chakraborty

2015

High Performance Integer Arithmetic Circuit Design on FPGA

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Dynamically reconfigurable FIR filter architectures with fast reconfiguration

Cited by 22 publications

References 20 publications

Sum-of-product architectures computing just right

Sum-of-product architectures computing just right

Techniques for Efficient Implementation of FIR and Particle Filtering

Design Automation and Case Studies

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