Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered

Cornelius, Claas; Koppe, S.; Timmermann, Dirk

doi:10.1109/icicdt.2006.220790

Cited by 10 publications

(6 citation statements)

References 7 publications

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“…In a cascaded chain of domino gates, footless topology is preferred for very-high-performance designs [2]. For this reason, only the footless domino logic circuits are described in this paper.…”

Section: Related Low Leakage Domino Circuitsmentioning

confidence: 99%

Low leakage dynamic circuits with dual threshold voltages and dual gate oxide thickness

Song

Wang

Yang

2007

2007 7th International Conference on ASIC

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In this paper, a low leakage circuit technique is proposed for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. NMOS sleep transistors and dual threshold voltages, dual gate oxide thickness CMOS technologies are utilized to place an idle domino circuit into a low leakage state. The proposed circuit technique lowers the total leakage power by up to 65.7% at a temperature of 110 and 94.1% at the room temperature as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 12.3% to 61.5% reduction in total leakage power is observed as compare to a previously published sleep switch scheme in a 45nm CMOS technology.

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Section: Related Low Leakage Domino Circuitsmentioning

confidence: 99%

Low leakage dynamic circuits with dual threshold voltages and dual gate oxide thickness

Song

Wang

Yang

2007

2007 7th International Conference on ASIC

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“…Hence, characteristic [1][2][3][4] of Domino circuits have been used in high performance critical circuits like microprocessors [5][6][7]. Dynamic CMOS logic has more advantage in terms of testability.…”

Section: Introductionmentioning

confidence: 99%

TSOP And TSON Testability Analysis And Realizations Of Domino VLSI CMOS Logic

Agrawal¹

2017

IJRASET

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The design for TSOP and TSON fault testability analysis and realizations of Domino VLSI CMOS Logic has been proposed. Domino VLSI CMOS circuits are fast dynamic CMOS circuits and hence suitable for fast and critical circuit applications. The proposed design beat the charge sharing difficulty with enhanced testability using faults TSOP and TSON. Furthermore, increase in number of transistors in the circuits, the proposed scheme shows uninterrupted power decrement in contrast to other schemes.

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“…Explicit handshaking blocks for small elements, such as bit adders, are expensive. Cornelius et al (2006) presented a new technique these dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuitTherefore, it is implicitly and efficiently managed using dual-rail carry propagation in adders. In this principle, logic flow in asynchronous circuits is mainly controlled by a request-acknowledgment handshaking protocol to establish a pipeline in the absence of clocks.…”

Section: Introductionmentioning

confidence: 99%

Area Efficient Self Timed Adders For Low Power Applications in VLSI

S.Bharathi¹

2015

IJIRSET

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ABSTRACT:In today"s world there is a great need for low power design and area efficient high performance in DIP (Digital Image Processing) systemIn this paper the proposed method presents a parallel single-rail self-timed adder. It uses recursive method for performing multi bit binary addition. This design attains good performance without any special speedup circuitry. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fan outs. The recursive method based adder consumes least power among other Self-timed adders. In our work this can be reduced with proposed adder. This technique presents a pre-processing and post processing adder to minimize the multiplier technique. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using cadence tool and superiority of the proposed approach over existing asynchronous adders. In this proposed system we are using a parallel prefix adder it is used to reduce the power consumption, area efficiently .Simulation of this technique is carried out by the cadence tool CADENCE GPDK 180nm Technology

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Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered

Cited by 10 publications

References 7 publications

Low leakage dynamic circuits with dual threshold voltages and dual gate oxide thickness

Low leakage dynamic circuits with dual threshold voltages and dual gate oxide thickness

TSOP And TSON Testability Analysis And Realizations Of Domino VLSI CMOS Logic

Area Efficient Self Timed Adders For Low Power Applications in VLSI

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