Low leakage dynamic circuits with dual threshold voltages and dual gate oxide thickness

Song, Yang; Wang, Hong; Yang, Zhijia

doi:10.1109/icasic.2007.4415569

Cited by 4 publications

References 2 publications

(2 reference statements)

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A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure

Kougianos

Mohanty

2015

Integration, the VLSI Journal

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a b s t r a c tOptimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology based integrated circuits for numerous reasons, including improving battery life of the system in which they are used as well as enhancing reliability. Leakage optimization at an early stage of the design cycle such as the registertransfer level (RTL) or architectural level provides more degrees of freedom to design engineers and ensures that the design is optimized at higher levels before proceeding to the next and more detailed phases of the design cycle. In this paper, an RTL optimization approach is presented that targets leakagepower optimization while performing simultaneous scheduling, allocation and binding. The optimization approach uses a nature-inspired firefly algorithm so that large digital integrated circuits can be effectively handled without convergence issues. The firefly algorithm optimizes the cost of leakage delay product (LDP) under various resource constraints. As a specific example, gate-oxide leakage is optimized using a 45 nm CMOS dual-oxide based pre-characterized datapath library. Experimental results over various architectural level benchmark integrated circuits show that average leakage optimization of 90% can be obtained. For a comparative perspective, an integer linear programming (ILP) based algorithm is also presented and it is observed that the firefly algorithm is as accurate as ILP while converging much faster. To the best of the authors' knowledge, this is the first ever paper that applies firefly based algorithms for RTL optimization.

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A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure

Kougianos

Mohanty

2015

Integration, the VLSI Journal

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Implementing low-power dynamic adders in MTCMOS technology

Rastogi

Pandey

2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-V T sleep transistor added, the leakage power of the circuits is also minimized by 94% to 96%. Simulation results verify that the circuits operate with high speed due to the low-V T CMOS Technology is widely used in all the digital circuits due to low power consumption. However the major component of power is contributed by leakage current, typically when the circuit is in idle mode. Sub-threshold leakage current is the major source of leakage current, especially in deep-submicron technologies [1]- [2]. As the technology is scaling down, the supply voltages are also being scaled down to minimize dynamic power consumption. With reducing supply voltages, the threshold voltage (V transistors used in the evaluation block and also achieve a significant reduction in leakage power. The ground bouncing noise of the eight bit MTCMOS TSPC adder is also evaluated. It is shown that the ground bouncing noise of the circuit reduces with increase in sleep signal rise delay.

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