DVGen: a test generator for the transmeta Efficeon VLIW processor

Rich, K.D.; Govindaraju, S.; Shaw, R. J.; Dobrikin, D.

doi:10.1109/hldvt.2005.1568820

Cited by 1 publication

(2 citation statements)

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“…DVGen can automatically and intelligently combine individual test specifications to produce new tests which concurrently test different corner cases, further increasing coverage. Details of the the process of test generation from a single transaction are available in [1]. In contrast, this paper focuses on how DVGen combines multiple test specifications to generate a single mix-test, and details how the tool address various inherent challenges.…”

Section: Introductionmentioning

confidence: 96%

“…The verification engineer is able to focus on test intent while writing high-level, minimally-constrained test specifications that target corner cases of the design. (A minimally-constrained test specification is one that specifies, or constrains, only what is necessary in order to achieve test intent, leaving other factors to be varied by the tool, details are available in [1].) DVGen generates self-checking tests that can be used in RTL simulation, emulation and on silicon.…”

Section: Introductionmentioning

confidence: 99%

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DVGen: Increasing Coverage by Automatically Combining Test Specifications

Rich¹,

Shaw²,

Govindaraju³

et al. 2006

2006 IEEE International High Level Design Validation and Test Workshop

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DVGen is a novel microprocessor test generator that allows the verification engineer to focus only on capturing test intent via minimally constrained test specifications. DVGen combines test specifications to generate tests that preserve the intent of each specification while causing the concurrent occurrence of interesting events from each specification. DVGen is very effective at uncovering multi-dimensional corner case bugs, which have historically been the bane of complex designs.

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Section: Introductionmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%