Dual material gate-graded channel-gate stack (DMG-GC-Stack) surrounding gate MOSFET: Analytical threshold voltage (V&lt;inf&gt;TH&lt;/inf&gt;) and subthreshold swing (S) models

Aouaj, Abdellah; Bouziane, Amal; Nouacry, A.

doi:10.1109/icmcs.2011.5945711

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…M1 is greater than work function of metal gate 2 (screening gate) M2 as shown in Fig. 5(b) [16] leading to V th1 >V th2 that can further enhance the gate transport efficiency.…”

Section: Impact Of Dual Materials Gate (Dmg) On Isesov Architectumentioning

confidence: 93%

Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications

Kumari

Saxena

Gupta

et al. 2012

16th International Workshop on Physics of Semiconductor Devices

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This paper investigates the potential of ISESOV architecture for low-voltage digital applications. A circuit analysis is performed for ISESOV MOSFET in terms of voltage transfer curve (VTC), supply current and noise margin and switching speed. These results are also compared with the ISE, SOV and bulk MOSFET architectures. Further improvement in the characteristic of inverter in terms of VTC and noise margin is observed by incorporating the gate stack architecture. The impact of Dual Material Gate architecture on the inverter performance has been also studied through exhaustive device simulations and it can be concluded that. ISESOV is a promising candidate for future digital applications as compared to ISE, SOV and bulk because it combines the advantages of both ISE and SOV architectures.

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“…M1 is greater than work function of metal gate 2 (screening gate) M2 as shown in Fig. 5(b) [16] leading to V th1 >V th2 that can further enhance the gate transport efficiency.…”

Section: Impact Of Dual Materials Gate (Dmg) On Isesov Architectumentioning

confidence: 93%

Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications

Kumari

Saxena

Gupta

et al. 2012

16th International Workshop on Physics of Semiconductor Devices

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“…Nanotechnology represents tremendous technological challenges that are exerting immense pressure on MOSFET to be further scaled to lower feature lengths [1][2]. The reduction of MOSFET dimension increases the short channel effects in the device [1].…”

Section: Introductionmentioning

confidence: 99%

Analytical Modeling of the Surface Potential of Triple Material Symmetrical Gate Stack Double Gate (TMGS-DG) MOSFET

Singh

Tripathi

2014

International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014)

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This paper presents two dimensional (2D) analytical Modeling of the Surface Potential of Triple Material Symmetric Gate Stack Double Gate (TMGS-DG) MOSFET. The model has been derived by solving 2D Poisson's equation in conjunction with suitable boundary conditions. The effect of high-k layer thickness on the potential barrier has been analyzed. The results obtained from the developed model have been compared with the numerical simulation results obtained using ATLAS TM device simulator.

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“…In Sharma et al [3], different gate engineering and channel engineering under DG-MOSFET technology are discussed, and also a comparison of various parameters among DG-DM, DG-GC, DG-GS-DM and DG-GS-GC is highlighted. Aouaj et al [7] and Bendib et al [8] discussed the concept of GC and GS on the double gate platform. In this work, we presented three types of device structures, DG-FD, DG-GC and DG-DI, by keeping speed in mind, as well as power consumption.…”

Section: Introductionmentioning

confidence: 99%

Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

Mohapatra¹,

Pradhan²,

Sahu³

2013

Transactions on Electrical and Electronic Materials

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When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current (I off ), on current (I on ), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

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Dual material gate-graded channel-gate stack (DMG-GC-Stack) surrounding gate MOSFET: Analytical threshold voltage (V<inf>TH</inf>) and subthreshold swing (S) models

Cited by 6 publications

References 11 publications

Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications

Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications

Analytical Modeling of the Surface Potential of Triple Material Symmetrical Gate Stack Double Gate (TMGS-DG) MOSFET

Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

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