Dual material gate field effect transistor (DMGFET)

Improvement in DC and pulse characteristics of AlGaN/GaN HEMT by employing dual metal gate structure

“…The mesa etching was done using Oxford reactive ion etching system with Cl 2 /BCl 3 based chemistry. Gate metal with dual metal structure is done in two steps involving the oblique angle deposition [11] of Nickel first then normal incidence deposition of Titanium metal followed by gold deposition. The thickness of Ni/Ti/Au is 45/45/150 nm.…”

“…Apart from passivation gate being the most critical element in these devices, gate contact engineering is one of the prominent technique used for melioration in these devices. Long et al [11,12] introduced the dual material gate field effect transistor and reported superior device performance on InGaP/InGaAs HFETs. It is well reported that using two different metals at the gate can bring improvement in terms of drain current, transconductance, and reduction of peak electric field [13] and also suppression of drain induced barrier lowering effect was reported using simulations of AlGaN/GaN dual metal gated high electron mobility transistors (DMG-HEMTs) [14].…”

Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I

“…Further, as the negative junction depth (NJD) increases (or the source/drain junction depth decreases), the potential barriers augment causing the degradation of drain current and threshold voltage. Recessed channel MOSFET, however, in conjunction with the structure incorporating gate electrode work function engineering such as dual material gate architecture [16][17][18][19], as shown in figure 1, enhances the drain current characteristics, average carrier velocity and suppresses SCEs [19], thereby proving superior to the SMG-RC MOSFET. With GEWE architecture, the step potential profile, due to different work functions of two metal gates, ensures reduction of SCEs and screening of the channel region under metal 1 from drain potential variations.…”

“…Devices with gate lengths down to 96 nm have also been demonstrated with grooved gates [21]. Although GEWE-RC MOSFET has not yet been fabricated, its fabrication may not pose any difficulty since several integration schemes (for dual material gate with bulk) have already been suggested in past such as tilt angle evaporation metal gate deposition [16], metal interdiffusion process [22], fully silicided metal gate [23] and chemical mechanical polishing [24]. As the CMOS processing technology is maturing and already into the 85 nm regime [25], fabricating a 50 nm gate length GEWE-RC should not hinder the possibility of achieving the potential benefits and excellent immunity against SCEs that the GEWE-RC MOSFET promises.…”

On-state and RF performance investigation of sub-50 nm L-DUMGAC MOSFET design for high-speed logic and switching applications

“…It is also responsible for the degradation of current driving capability and threshold voltage. The concave MOSFET, however, in conjunction with dual material gate (DMG) architecture [12][13][14], as shown in figure 1, enhances drain current characteristics, average carrier velocity and suppresses SCEs, thereby proving superior to the conventional concave MOSFET. With DMG architecture, the step potential profile, due to different work functions of two metal gates, ensures reduction of SCEs and screening of the channel region under metal 1 from drain potential variations.…”