Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I

Abstract

This paper discusses a threshold voltage model for novel device structure: gate electrode work function engineered recessed channel (GEWE-RC) nanoscale MOSFET, which combines the advantages of both RC and GEWE structures. In part I, the model accurately predicts (a) surface potential, (b) threshold voltage and (c) sub-threshold slope for single material gate recessed channel (SMG-RC) and GEWE-RC structures. Part II focuses on the development of compact analytical drain current model taking into account the transition regimes from sub-threshold to saturation. Furthermore, the drain conductance evaluation has also been obtained, reflecting relevance of the proposed device for analogue design. The analysis takes into account the effect of gate length and groove depth in order to develop a compact model suitable for device design. The analytical results predicted by the model confirm well with the simulated results. Results in part I also provide valuable design insights in the performance of nanoscale GEWE-RC MOSFET with optimum threshold voltage and negative junction depth (NJD), and hence serves as a tool to optimize important device and technological parameters for 40 nm technology.

Gate electrode stacked source/drain SON trench MOSFET for biosensing application

“…A dual metal (DM) gate with a nano-cavity length (l nc ) of 8 nm, oxide-thickness (t ox ) of 2 nm, and gate length (L G ) of 20 nm is implemented in the proposed biosensor [23]. As the implementaion of higher gate workfunction near to the source end offers an improve sensitivity for which the metal workfunction of M1 = 4.7 eV, and M2 = 4.1 eV are being considered in the gate region [35,37]. Again the specification of the stack source/drain formed by silicon and germanium material is taken as reported in [40].…”

“…However, the transport efficiency of the recessed channel (RC) MOS deteriorates due to the presence of the groove corner which affects the device threshold voltage. Therefore with the help of workfunction engineering and stack source/drain, the channel field can be improved to boost the carrier transport efficiency that may give better sensitivity for biosensors [34][35][36][37]. Now a days, the silicon-on-insulator (SOI) technique provides a better isolation between channel and body to enhance the device SCEs.…”