On-state and RF performance investigation of sub-50 nm L-DUMGAC MOSFET design for high-speed logic and switching applications

Abstract

In this paper, an extensive study on the on-state, switching and RF performance of a laterally amalgamated dual material gate concave (L-DUMGAC) MOSFET and the influence of technology variations such as gate length, negative junction depth (NJD) and gate bias on the device's behavior is performed using an ATLAS device simulator. Simulations reveal that the L-DUMGAC design exhibits a significant enhancement in the device's switching characteristics in terms of reduced on-resistance and, hence, the reduced conduction power loss, switching loss and enhanced on-current, I ON. Further, the L-DUMGAC design is studied for the RF application circuit design by examining the stability, cutoff frequency, power gains and the parasitic capacitances. The results are, thus, useful for optimizing the performance and reliability of nanoscale L-DUMGAC MOSFETs for high-speed logic, switching and RF applications.

Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I

“…With GEWE architecture, the step potential profile, due to different work functions of two metal gates, ensures reduction of SCEs and screening of the channel region under metal 1 from drain potential variations. Thus, the average electric field in the channel is enhanced, improving the electron velocity near the source and hence the carrier transport efficiency [19]. Further, the GEWE-RC MOSFET design exhibits superior distortion and linearity behaviour [20] in comparison with RC MOSFET, imperative for low-noise applications and RFICs design, in terms of figure-of-merit (FOM) metrics: V I P 2 , V I P 3 , IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3.…”

“…Further, as the negative junction depth (NJD) increases (or the source/drain junction depth decreases), the potential barriers augment causing the degradation of drain current and threshold voltage. Recessed channel MOSFET, however, in conjunction with the structure incorporating gate electrode work function engineering such as dual material gate architecture [16][17][18][19], as shown in figure 1, enhances the drain current characteristics, average carrier velocity and suppresses SCEs [19], thereby proving superior to the SMG-RC MOSFET. With GEWE architecture, the step potential profile, due to different work functions of two metal gates, ensures reduction of SCEs and screening of the channel region under metal 1 from drain potential variations.…”