Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Lee, Chang-Kyo; Lee, Jun-Ha; Kim, Kiho; Heo, Jeong Wook; Baek, Jin-Hyeok; Cha, Gil-Hoon; Lee, Dong Hun; Park, Jong‐Wook; Lee, Seunseob; Cho, Si-Hyeong; Choi, YoungRok; Ha, Kwang Soon; Seo, Eunsung; Park, Younsik; Bae, Seung-Jun; Song, Indal; Hyun, Seok-Hun; Kwon, Hyeokshin; Sohn, Young-Soo; Choi, Jung-Hwan; Park, Kwang-Il; Jang, Seong-Jin

doi:10.1109/jssc.2018.2850937

Cited by 12 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In conventional sampling network with a dynamic comparator, a sampling capacitor ( C IN ) is shared for both input signal and reference sampling. Thereby, the kick‐back effect by the un‐balanced impedance in the sampling network causes additional offset (3‐ σ : 21 mV in this design) [15], which limits the resolution assign in the pipelined ADC. To remove the additional offset in the proposed design, the additional capacitor ( C REF ) for reference voltage is newly assigned.…”

Section: Circuit Implementationmentioning

confidence: 99%

Noise analysis of replica driving technique and its verification to 12‐bit 200 MS/s pipelined ADC

Lee

Ryu

2019

IET Circuits, Devices & Systems

Self Cite

View full text Add to dashboard Cite

This study demonstrates the noise analysis of a replica driving MDAC architecture, which is verified by implementing a 12-bit 200 MS/s replica driving pipelined analogue-to-digital converter (ADC). Based on the noise design strategy with the target effective number of bits = 10.5-bit, the overall dynamic performance degradation by KT/C noise and thermal noise by an amplifier is alleviated by removing the front-end sample-and-hold (S/H) circuit, and the transconductance (g m) of the inner source follower is maximised by increasing the current and threshold voltage (V T) reduction. Replica input sampling networks are designed for the first-stage sub-ADC and the first-stage MDAC with different aspect ratios to minimise the sampling skew for the S/H-less architecture. A prototype 12-bit 200 MS/s ADC is fabricated in a 65 nm complementary metal oxide semiconductor. The measured spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) at a 1.0 MHz input signal is 82.6 and 65.6 dB, respectively, and SFDR and SNDR at the Nyquist (=99.0 MHz) input are 77.3 and 58.6 dB, respectively. The ADC core and the reference driver consume 53.9 and 13.2 mW, respectively, at a 1.2 V supply voltage.

show abstract

Section: Circuit Implementationmentioning

confidence: 99%

Noise analysis of replica driving technique and its verification to 12‐bit 200 MS/s pipelined ADC

Lee

Ryu

2019

IET Circuits, Devices & Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…Comparators are omnipresent building blocks in mixed-signal systems. Applications such as memories [1][2][3], data receivers [4][5][6], and Analog-to-Digital Converters (ADCs) [7][8][9] necessitate high speed, low noise/offset, yet power-and area-efficient designs. Their role in ADCs (Successive Approximation Register (SAR), flash, pipeline) ( Figure 1) is of special importance, since they need to accurately translate small analog signals into digital information.…”

Section: Introductionmentioning

confidence: 99%

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

View full text Add to dashboard Cite

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

show abstract

A Low Noise 10-Bit 59.41dB SNR SAR ADC Using Chopper Comparator for Biomedical Applications

Pham,

Nguyen,

et al. 2024

Lecture Notes in Networks and Systems

View full text Add to dashboard Cite

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Cited by 12 publications

References 8 publications

Noise analysis of replica driving technique and its verification to 12‐bit 200 MS/s pipelined ADC

Noise analysis of replica driving technique and its verification to 12‐bit 200 MS/s pipelined ADC

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

A Low Noise 10-Bit 59.41dB SNR SAR ADC Using Chopper Comparator for Biomedical Applications

Contact Info

Product

Resources

About