Dual‐Gated MoS₂ Memtransistor Crossbar Array

Abstract

Memristive systems offer biomimetic functions that are being actively explored for energy-efficient neuromorphic circuits. In addition to providing ultimate geometric scaling limits, 2D semiconductors enable unique gatetunable responses including the recent realization of hybrid memristor and transistor devices known as memtransistors. In particular, monolayer MoS 2 memtransistors exhibit nonvolatile memristive switching where the resistance of each state is modulated by a gate terminal. Here, further control over the memtransistor neuromorphic response through the introduction of a second gate terminal is gained. The resulting dual-gated memtransistors allow tunability over the learning rate for non-Hebbian training where the long-term potentiation and depression synaptic behavior is dictated by gate biases during the reading and writing processes. Furthermore, the electrostatic control provided by dual gates provides a compact solution to the sneak current problem in traditional memristor crossbar arrays. In this manner, dual gating facilitates the full utilization and integration of memtransistor functionality in highly scaled crossbar circuits. Furthermore, the tunability of long-term potentiation yields improved linearity and symmetry of weight update rules that are utilized in simulated artificial neural networks to achieve a 94% recognition rate of handwritten digits.

Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates

“…This is the typical behaviour of an electronic synapse, where the decreasing of conductance is attributed to potentiation, while the conductance increase is attributed to synapse depression [21,22]. A comparison of our results with similar results obtained for a dual-gate memtransistor having MoS 2 as channel instead of graphene monolayer [8] is presented in Table 2. The parameters taken into account are the maximum drain current, I D,max , the maximum voltage values for the top and back gates, V TG,max and V BG,max , the maximum drain voltage, V D,max , the on-off ratio, and the memory window.…”

“…This drain voltage value can decrease by up to 12 V by introducing top gate configurations [6] or using localized beam irradiation techniques [7]. Additionally, recent crossbar arrays of MoS 2 memtransistors incorporating an array of 10 × 10 FETs [8,9] have been reported, paving the way for memtransistor applications in resistive memories and neuromorphic computation.…”

Variability and Yield in h‐BN‐Based Memristive Circuits: The Role of Each Type of Defect

“…However, refs. [ 6–10 ] used high temperatures (≈800 °C) during the fabrication of the devices, which is not compatible with back‐end‐of‐line (BEOL) processes, as these do not permit temperatures >450 °C. [ 11,12 ] Furthermore, in all the aforementioned studies the current flows horizontally along the 2D‐LM (i.e., in‐plane), and it has been demonstrated that grain boundaries (GB), [ 13 ] wrinkles, [ 14 ] and polymer residues [ 15 ] can remarkably alter the properties of the devices in an uncontrollable way.…”

Programmable terahertz metamaterials with non-volatile memory

“…Furthermore, the hysterical effect has been found in a multitude of materials, such as PCM, twodimensional materials 22,27 , perovskite 28,29 . By integrating these materials into the metadevices, the SLM capable of multi-state storage is extendable to a broad frequency range from microwave to visible light.…”