Variability and Yield in h‐BN‐Based Memristive Circuits: The Role of Each Type of Defect

Shen, Yaqing; Zheng, Wei; Zhu, Kaichen; Xiao, Yanhe; Wen, Chao; Liu, Yingwen; Xu, Jun; Lanza, Mario

doi:10.1002/adma.202103656

Cited by 71 publications

(98 citation statements)

References 34 publications

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“…Note that as PdSe 2 nanosheets are transferred onto the bottom Au electrode, the nanosheets may be slightly delaminated from the electrode during the sample preparation process, causing a gap to form. [27,36,43] d) I-V curves during 100 measurement cycles and e) the corresponding histogram of the set and reset voltage distributions (C V : coefficient of variation, C V = σ/µ, where σ and µ are the standard deviation and mean value of operating voltage, respectively). Before the repeated I-V cycles, an electroforming process with a positive voltage of ≈1.8 V is needed.…”

Section: Uniform Resistive Switching In Memristors With Ultrathin Het...mentioning

confidence: 99%

In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeO_x/PdSe₂ Heterostructure

Chen

et al. 2022

Advanced Materials

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between the two subsystems. To push the envelope for speed and energy efficiency, a radically different computing paradigm that allows in situ computation within the memory, or in-memory computing (IMC), is revolutionary to address the issues associated with abundant data movement. [2,3] In particular, IMC based on analog memristors holds promise to provide a low latency and energy-efficient approach to implement data-centric applications such as image processing by means of neural network training. [3,4] Thus far, the development of convolutional neural network (CNN), an important model for image recognition, has been experimented using memristor devices, which are plagued with fundamental scientific issues related to interdevice variability, nonlinearity, and sneak path current. [5][6][7] Such a twoterminal memristor is typically integrated with metal oxide as a switching medium, which relies on the formation and rupture of filaments in the amorphous medium for resistive switching (RS). [5,6,[8][9][10][11][12] However, the stochasticity of the ions' movement is difficult to control and thus results in poor spatial and temporal variations in the RS performance. [13][14][15] The variation has a significant influence on the computing accuracy loss, as most reported high computing accuracies were only realized with small cycleto-cycle variation. [7,13,16] Compared with single-layered oxide, switching medium made of double-layered oxide offers betterIn-memory computing based on memristor arrays holds promise to address the speed and energy issues of the classical von Neumann computing system. However, the stochasticity of ions' transport in conventional oxidebased memristors imposes severe intrinsic variability, which compromises learning accuracy and hinders the implementation of neural network hardware accelerators. Here, these challenges are addressed using a low-voltage memristor array based on an ultrathin PdSeO x /PdSe 2 heterostructure switching medium realized by a controllable ultraviolet (UV)-ozone treatment. A distinctively different ions' transport mechanism is revealed in the heterostructure that can confine the formation of conductive filaments, leading to a remarkable uniform switching with low set and reset voltage variability values of 4.8% and −3.6%, respectively. Moreover, convolutional image processing is further implemented using various crossbar kernels that achieve a high recognition accuracy of ≈93.4% due to the highly linear and symmetric analog weight update as well as multiple conductance states, manifesting its potential beyond von Neumann computing.

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Section: Uniform Resistive Switching In Memristors With Ultrathin Het...mentioning

confidence: 99%

In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeO_x/PdSe₂ Heterostructure

Chen

et al. 2022

Advanced Materials

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“…In a recent study, this was scaled up to 100 × 100 crossbar array of Au/h-BN/Au cells with lateral size of 320 nm × 420 nm; this is the largest circuit based on 2D materials ever reported, both in terms of number of devices and integration density. [176] Recently, our group successfully fabricated micro-supercapacitor arrays using 4 in. 2D Ti 3 C 2 T x MXene films prepared by spray coating.…”

Section: Microscale and Nanoscale Device Integrationmentioning

confidence: 99%

“…In a recent study, this was scaled up to 100 × 100 crossbar array of Au/h‐BN/Au cells with lateral size of 320 nm × 420 nm; this is the largest circuit based on 2D materials ever reported, both in terms of number of devices and integration density. [ 176 ]…”

Section: Applications Of Wafer‐scale Vdw 2d Materialsmentioning

confidence: 99%

Growth of 2D Materials at the Wafer Scale

Guo

Kim

et al. 2022

Advanced Materials

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der Waals (vdW) layered 2D materials are regarded as a very promising new material system to support postsilicon IC technologies because of their rich and excellent physical properties even with thickness at the atomic scale (<1 nm). [1][2][3] It has been reported that monolayer MoS 2 as a transistor channel can be effectively controlled using 1 nm length carbon nanotube gating. Electric field control on such a short channel can achieve MoS 2 transistors with excellent performance, including an on/off current ratio up to 10 6 and a subthreshold swing (SS) of 65 mV s −1 . [4] This indicates that 2D vdW semiconductors are promising candidates to replace silicon for continued downscaling.Many vdW layered 2D materials have been synthesized and explored since the graphene discovery in 2004. They include highly conductive graphene [1] and MXenes (atomic-thin transition metal carbides and nitrides), [5] transition metal chalcogenides (TMDCs, including both metallic [6] and semiconducting [2] ), 2D elemental semiconductors (black phosphorus (BP), [7] tellurium (Te) [8] ), 2D insulators (e.g., hexagonal boron nitride (h-BN) [9] and some oxides). [10] The large variety of vdW layered 2D materials provides a large potential for advanced 2D electronics.However, for scalable applications, all vdW layered 2D materials face a common challenge: transitioning from micrometer-scale 2D flakes to wafer-scale. [1,2,[11][12][13] This is necessary for scaling up 2D vdW materials application in the high-end semiconductor industry. The history of silicon wafer development and its significant impact on modern information technologies has already demonstrated the importance of a large wafer size for volume production at an acceptable cost. Some materials, such as graphene, [14] h-BN, [15] and TMDCs, [16] have been heavily explored for wafer-scale growth, but the reality is that wafer-scale film quality still has enormous space to improve, especially when compared to chip-grade single-crystalline silicon. Other materials such as MXenes, BP, Te, and vdW oxides, have only a few reported papers focusing on their wafer-scale growth. Hence, we feel that this timely review focusing on wafer-scale growth methods of relevant 2D vdW layered materials is urgently needed.The scope of this review is clarified in Figure 1, where the structures, properties, wafer-scale growth methods, and applications of representative vdW layered 2D materials. We begin by briefly introducing these 2D vdW layered materials and discuss Wafer-scale growth has become a critical bottleneck for scaling up applications of van der Waal (vdW) layered 2D materials in high-end electronics and optoelectronics. Most vdW 2D materials are initially obtained through top-down synthesis methods, such as exfoliation, which can only prepare small flakes on a micrometer scale. Bottom-up growth can enable 2D flake growth over a large area. However, seamless merging of these flakes to form large-area continuous films with well-controlled layer thickness and lattice orientation is still a sign...

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“…a) Yield and redundancy: High yield and redundancy are required for the use of crossbars as memories. Redundancy is essential in applications where data recovery becomes important [31], [32], and in-memory computing should be highly accurate.…”

Section: B Programming Nonlinearitymentioning

confidence: 99%

Variability-Aware Memristive Crossbars—A Tutorial

James

Chua

2022

IEEE Trans. Circuits Syst. II

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Memristor crossbar architecture is one of the most popular circuit configurations due to its wide range of practical applications. The crossbar architecture can emulate the weighted summation operation, called multiply and accumulate operation (MAC). The errors to MAC computing get introduced due to a range of crossbar variability. We broadly group the variability in three categories: (1) device-to-device variations, (2) programming nonlinearity, and (3) those from peripheral circuits. This tutorial provides insights into the variability and compensation approaches that can be adopted to reduce its impact when designing for practical applications with crossbars. .

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Variability and Yield in h‐BN‐Based Memristive Circuits: The Role of Each Type of Defect

Cited by 71 publications

References 34 publications

In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeO_x/PdSe₂ Heterostructure

In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeO_x/PdSe₂ Heterostructure

Growth of 2D Materials at the Wafer Scale

Variability-Aware Memristive Crossbars—A Tutorial

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Variability and Yield in h‐BN‐Based Memristive Circuits: The Role of Each Type of Defect

Cited by 71 publications

References 34 publications

In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeOx/PdSe2 Heterostructure

In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeOx/PdSe2 Heterostructure

Growth of 2D Materials at the Wafer Scale

Variability-Aware Memristive Crossbars—A Tutorial

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In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeO_x/PdSe₂ Heterostructure

In‐Memory Computing using Memristor Arrays with Ultrathin 2D PdSeO_x/PdSe₂ Heterostructure