The research field of metasurfaces has attracted considerable attention in recent years due to its high potential to achieve flat, ultrathin optical devices of high performance. Metasurfaces, consisting of artificial patterns of subwavelength dimensions, often require fabrication techniques with high aspect ratios (HARs). Bosch and Cryogenic methods are the best etching candidates of industrial relevance towards the fabrication of these nanostructures. In this paper, we present the fabrication of Silicon (Si) metalenses by the UV-Nanoimprint Lithography method and cryogenic Deep Reactive Ion Etching (DRIE) process and compare the results with the same structures manufactured by Bosch DRIE both in terms of technological achievements and lens efficiencies. The Cryo- and Bosch-etched lenses attain efficiencies of around 39% at wavelength λ = 1.50 µm and λ = 1.45 µm against a theoretical level of around 61% (for Si pillars on a Si substrate), respectively, and process modifications are suggested towards raising the efficiencies further. Our results indicate that some sidewall surface roughness of the Bosch DRIE is acceptable in metalense fabrication, as even significant sidewall surface roughness in a non-optimized Bosch process yields reasonable efficiency levels.

This study presents the design and manufacture of metasurface lenses optimized for focusing light with 1.55 µm wavelength. The lenses are fabricated on silicon substrates using electron beam lithography, ultraviolet-nanoimprint lithography and cryogenic deep reactive-ion etching techniques. The designed metasurface makes use of the geometrical phase principle and consists of rectangular pillars with target dimensions of height h = 1200 nm, width w = 230 nm, length l = 354 nm and periodicity p = 835 nm. The simulated efficiency of the lens is 60%, while the master lenses obtained by using electron beam lithography are found to have an efficiency of 45%. The lenses subsequently fabricated via nanoimprint are characterized by an efficiency of 6%; the low efficiency is mainly attributed to the rounding of the rectangular nanostructures during the pattern transfer processes from the resist to silicon due to the presence of a thicker residual layer.

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In this paper, we present for the first time a field-effect-transistor (FET) having a 10 nm thick tin sulfide (SnS) channel fabricated at the wafer scale with high reproducibility. SnS-based FETs are in on-state for increasing positive back-gate voltages up to 6 V, whereas the off-state is attained for negative back-gate voltages not exceeding −6 V, the on/off ratio being in the range 102–103 depending on FET dimensions. The SnS FETs show a subthreshold slope (SS) below 60 mV/decade thanks to the in-plane ferroelectricity of SnS and attaining a minimum value SS = 21 mV/decade. Moreover, the low SS values can be explained by the existence of a negative value of the capacitance of the SnS thin film up to 10 GHz (for any DC bias voltage between 1 and 5 V), with the minimum value being −12.87 pF at 0.1 GHz.

As metasurfaces begin to find industrial applications there is a need to develop scalable and cost-effective fabrication techniques which offer sub-100nm resolution while providing high throughput and large area patterning. Here we demonstrate the use of UV-Nanoimprint Lithography and Deep Reactive Ion Etching (Bosch and Cryogenic) towards this goal. Robust processes are described for the fabrication of silicon rectangular pillars of high pattern fidelity. To demonstrate the quality of the structures, metasurface lenses, which demonstrate diffraction limited focusing and close to theoretical efficiency for NIR wavelengths λ ∈ (1.3 μm, 1.6 μm), are fabricated. We demonstrate a process which removes the characteristic sidewall surface roughness of the Bosch process, allowing for smooth 90-degree vertical sidewalls. We also demonstrate that the optical performance of the metasurface lenses is not affected adversely in the case of Bosch sidewall surface roughness with 45 nm indentations (or scallops). Next steps of development are defined for achieving full wafer coverage.