DRAM Yield Analysis and Optimization by a Statistical Design Approach

Li, Yan; Schneider, Helmut; Schnabel, Florian; Thewes, R.; Schmitt‐Landsiedel, D.

doi:10.1109/tcsi.2011.2157741

Cited by 46 publications

(28 citation statements)

References 18 publications

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“…However, the retention time of each DRAM cell is strongly affected by the value stored both in that cell and in nearby cells due to circuit-level crosstalk effects [21,26]. We find that, in some devices, testing with all 1s and all 0s identifies less than 15% of all weak cells.…”

Section: Introductionmentioning

confidence: 87%

“…In this data pattern, consecutive bits alternate between 0 and 1. In DRAM circuit architectures where adjacent bits are mapped to adjacent cells, checkerboard patterns may induce worse retention time behavior than patterns of all 1s or 0s [21]. Intuitively, this is because bitline coupling noise increases with the voltage difference between the coupled bitlines, and storing alternating values in consecutive bitlines maximizes the voltage difference between each bitline and its immediate neighbors.…”

Section: Data Patterns Testedmentioning

confidence: 99%

“…However, coupling with other nearby bitlines can also exist. Hence, even worse retention time behavior may be triggered when a single cell storing V DD is surrounded by cells storing 0 V [21]. This data pattern attempts to efficiently approximate this scenario.…”

Section: Data Patterns Testedmentioning

confidence: 99%

“…Al-Ars et al [2] performed analysis and simulation studies to examine the interaction between different DRAM circuit architectures and bitline coupling noise. Li et al [21] performed a similar analysis in their development of a DRAM reliability model. None of these works show the impact of bitline coupling on retention time.…”

Section: Data Pattern Dependencementioning

confidence: 99%

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An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

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DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperaturecontrolled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

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Section: Introductionmentioning

confidence: 87%

Section: Data Patterns Testedmentioning

confidence: 99%

Section: Data Patterns Testedmentioning

confidence: 99%

Section: Data Pattern Dependencementioning

confidence: 99%

See 2 more Smart Citations

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

View full text Add to dashboard Cite

show abstract

“…DRAM cells are affected by process variation in two major aspects: (i) cell capacitance and (ii) cell resistance. Although every cell is designed to have a large capacitance (to hold more charge) and a small resistance (to facilitate the flow of charge), some deviant cells may not be manufactured in such a manner [15,26,29,30,38,41,42]. In Figure 4a, we illustrate the impact of process variation using two different cells: one is a typical cell conforming to design (left column) and the other is the worst-case cell deviating the most from design (right column).…”

Section: Process Variation: Cells Are Not Created Equalmentioning

confidence: 99%

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

191

328

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In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85• C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55• C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case.Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55• C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adaptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface.We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.

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