DearDRAM: Discard Weak Rows for Reducing DRAM’s Refresh Overhead

Zhan, Xusheng; Bao, Yungang; Sun, Ninghui

doi:10.1007/978-981-13-2423-9_9

Cited by 2 publications

(2 citation statements)

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“…Many studies 13,21 work on exploiting the weak rows by skipping their refreshes in order to reduce the number of refresh operations in DRAM. Here, in the majority of the cases, the refresh interval is increased without considering the issues of less numbered weak rows.…”

Section: Related Workmentioning

confidence: 99%

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WinDRAM: Weak rows as in‐DRAM cache

Kumar

Sinha

Das

2022

Concurrency and Computation

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The primary factor responsible for increasing the refresh rate is the presence of weak rows in a DRAM. They have a shorter retention time and lose charge faster than regular rows. Recently, a technique known as in-DRAM cache was introduced in which some DRAM rows act as a separate module. The in-DRAM cache can be used for a variety of purposes in DRAM. We present WinDRAM, an in-DRAM cache comprised of all the DRAM's weak rows. The most recently accessed rows are copied into the in-DRAM cache so that when the row is accessed again, both rows (original and copy) can be activated at the same time. Such simultaneous activation reduces activation time and, as a result, DRAM access latency. Dual-row activation is the term for this concept. Because weak rows are part of the in-DRAM cache and are frequently accessed, WinDRAM does not perform a periodic refresh on them. Existing techniques based on in-DRAM cache do not design the in-DRAM cache using weak rows. WinDRAM proposes a novel idea by designing the in-DRAM cache using weak rows. Because the weak rows do not need to be refreshed, the refresh interval of the remaining rows can be increased, resulting in a refresh rate reduction of 80% to 90%. The speedup is 15% to 25% faster than standard DRAM and 12.77% faster than previous work for high memory-intensive workloads. Overall energy consumption is also reduced by 10% to 15%. K E Y W O R D SDRAM refresh, dual-row activation, in-DRAM cache, weak row INTRODUCTIONModern, high-performance computers require both on-chip and off-chip memory designs that are efficient. As the number of cores in modern multi-core systems increases, the need for bigger and more efficient main memory becomes crucial. With shrinking technological sizes, it becomes simpler to construct greater main memory as memory density increases. 1 However, it becomes increasingly difficult to reduce the energy consumption and access latency of such large memory. 1 Due to its improved density and capacity as well as its low production costs, DRAM has become the primary component of most contemporary main memories. 2,3 Typically, a DRAM bank is partitioned into many subarrays, as described in Section 2.Each subarray stores several DRAM cells in a 2D fashion (having rows and columns). Each DRAM cell is responsible for storing a single bit of data.The capacitor included within the cell stores the bit as a charge. For instance, a completely charged capacitor indicates that the cell contains bit 1.However, DRAM cells are leaky and lose their charge over a period of time (retention time). To keep the data contained within these cells, periodic refresh procedures must be done. Due to the recent increase in memory-intensive applications, the DRAM is being increased to meet their requirements. Consequently, the energy required to retain the data in the DRAM cells via periodic refresh increases essentially with the size of the main memory. 1 Refresh activities in a DRAM are accountable for up to fifty percent of the DRAM's power consumption. 4,5 In addition, these opera...

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Section: Related Workmentioning

confidence: 99%

“…DearDRAM is focused on disabling or ignoring the weak rows during refresh as the refresh overhead of the DRAM with the weak rows was too high 21 . It succeeds in reducing the refresh interval from 64 ms with weak rows to 256 ms without them.…”

Section: Related Workmentioning

confidence: 99%