Drain Side Area-Modulation Effect of Parasitic Schottky Diode on ESD Reliability for High Voltage P-Channel Lateral-Diffused MOSFETs

Hong, Shi-Zhe; Chen, Shen-Li; Chen, Hung-Wei; Lee, Yi-Mu

doi:10.1109/led.2021.3104735

Cited by 3 publications

(2 citation statements)

References 20 publications

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“…Thus, primitive logic gates are made by utilizing diodes and resistors. While transistors, the other major type of nonlinear devices, make up the majority of devices in digital logic, diodes are indispensable, e.g., to protect chips from electrostatic discharge (ESD), , to bridge electronics with optics (as photodetectors) − and in analog circuits to perform logarithmic operation. − These applications not only ensure proper working conditions for the digital circuitry but also extend capability of the chip as mixed-signal circuits, and further as photonic-interconnected chips, leading to futuristic more-than-Moore integrated circuits (ICs) …”

Section: Introductionmentioning

confidence: 99%

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping

Zhang,

Sun,

Wei

et al. 2024

ACS Nano

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Diodes based on p−n junctions are fundamental building blocks for numerous circuits, including rectifiers, photovoltaic cells, light-emitting diodes (LEDs), and photodetectors. However, conventional doping techniques to form por n-type semiconductors introduce impurities that lead to Coulomb scattering. When it comes to low-dimensional materials, controllable and stable doping is challenging due to the feature of atomic thickness. Here, by selectively depositing dielectric layers of Y 2 O 3 and AlN, direct formation of waferscale carbon-nanotube (CNT) diodes are demonstrated with high yield and spatial controllability. It is found that the oxygen interstitials in Y 2 O 3 , and the oxygen vacancy together with Al− Al bond in AlN/Y 2 O 3 electrostatically modulate the intrinsic CNTs channel, which leads to p-and n-type conductance, respectively. These CNTs diodes exhibit a high rectification ratio (>10 4 ) and gate-tunable rectification behavior. Based on these results, we demonstrate the applicability of the diodes in electrostatic discharge (ESD) protection and photodetection.

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Section: Introductionmentioning

confidence: 99%

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping

Zhang,

Sun,

Wei

et al. 2024

ACS Nano

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show abstract

“…Because junctionless transistors don't have source and drain junctions, they don't need to build ultra-steep junctions 7 or do a lot of thermal annealing 8 for S/D dopant activation is a significant advantage. Also, the fabrication process is easier because there are no lateral diffused drains, 9 pocket implantations, 10 or shallow junctions anymore. With device size reduced, device dependability becomes a concern.…”

mentioning

confidence: 99%

A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

Raut

Nanda

2022

ECS J. Solid State Sci. Technol.

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This article proposes an analytical charge-based model that incorporates interface trapping. The model's applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with TCAD device simulation results and available experimental data from the literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction-Less Field Effect Transistor (GAAJLFET) with SiO2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device's characteristics without impairing the performance, a suitable device with SiO2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO2 as a gate insulator. A GAAJLFET with SiO2 as an insulating material has very different device parameters than a GAAJLFET with SiO2 and high-k gate-stack as a gate insulating material.

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Establishment of analytical model for electrostatic discharge gate-to-source capacitance of power metal-oxide-semiconductor field-effect transistor

Su,

Wang,

Tan

et al. 2024

Acta Phys. Sin.

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In the actual HBM test, it is found that the ESD test results of various power MOSFET devices show asymmetry between forward and reverse withstand voltages, while the ESD process does not distinguish between positive and negative directions. Large differences in forward and reverse withstand voltages are unacceptable for power MOSFETs or as ESD protection devices. The problem of its causing device failure is particularly pronounced. In this paper, by establishing the analytical model of gate to source capacitance of SGT-MOSFET, VUMOSFET and VDMOS under the forward and reverse voltages, we comparatively analyze the reasons for the asymmetry of the forward and reverse withstand voltages and their different ratios of the three kinds of power MOSFET, which provides a theoretical basis for the testing of the device's ESD and the analysis of its reliability. It is found that the ESD forward and reverse withstand voltage asymmetry phenomenon of different power MOSFET structures is related to the variation of gate to source capacitance caused by the reverse-type layer. When a forward voltage is applied between the gate and source, the device gate to source capacitance consists of the oxide layer capacitance around the gate in parallel; when a reverse voltage is applied, the gate to source capacitance consists of the virtual gate to drain capacitance in series with the inverse layer capacitance and then in parallel with the other oxide layer capacitance around the gate. This results in a decrease in the gate to source capacitance at the reverse voltage, making the device reverse withstand voltage greater than the forward withstand voltage. The difference in the ratio of ESD reverse withstand voltage to forward withstand voltage for different devices is related to the change in the capacitance of the inverse layer in the gate to source capacitor under reverse voltage caused by the difference in device structure.

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Drain Side Area-Modulation Effect of Parasitic Schottky Diode on ESD Reliability for High Voltage P-Channel Lateral-Diffused MOSFETs

Cited by 3 publications

References 20 publications

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping

A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

Establishment of analytical model for electrostatic discharge gate-to-source capacitance of power metal-oxide-semiconductor field-effect transistor

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