Drain current - gate voltage characteristics of Si MOSFETs fabricated on Si-on-SiC wafers

Araki, Ryosuke; Shimizu, Hideo; Kurumi, Takamasa; Kinoshita, Hiroyuki; Yoshimoto, Masahiro

doi:10.1109/imfedk.2011.5944848

Cited by 7 publications

(4 citation statements)

References 3 publications

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“…1). The Si material, which can be made by the bonding process on top of SiC [11, 12], is used to form the channel and ohmic contact for the source electrode. When VDMOS structure is turned off, the highest electric field is produced at the interface of the P‐base and N‐type drift region (area A in Fig.…”

Section: Device Structure and Descriptionmentioning

confidence: 99%

“…After annealing, the Si layer of the wafer is ground and polished to form SiC/Si VDMOS. Although off–state current of SiC/Si VDMOS is slightly degraded due to the bonded SiC/Si heterojunction, the leakage is as small as a value less than an order of nA/mm [11]. This level of leakage current does not affect the breakdown characteristics of SiC/Si VDMOS.…”

Section: Device Structure and Descriptionmentioning

confidence: 99%

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SiC/Si heterojunction VDMOS breaking silicon limit by breakdown point transfer technology

Duan

Zhao

et al. 2018

Micro & Nano Letters

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An innovative semiconductor power vertical double-diffused MOSFET (VDMOS) is proposed for the first time with the SiC/Si heterojunction at the P-base and N-drift region (called for SiC/Si VDMOS), which improves the trade-off between the breakdown voltage (BV) and specific on-resistance (R on,sp). The 'soft' Si material has been combined with the 'hard' SiC material to play their own advantages for SiC/Si VDMOS. The Si has been formed above the 6H-SiC substrate to make up the channel and source electrode, and the 6H-SiC is underneath the P-base to form the SiC/Si heterojunction. The novel terminal technology of breakdown point transfer has been advanced for the first time and applied to SiC/Si VDMOS, which transfers the breakdown point of SiC/Si VDMOS and improve the BV compared with Si VDMOS. The simulated results have been shown that the optimised BV of proposed SiC/Si VDMOS is increased from 226 to 578 V compared with the conventional Si VDMOS with the same drift region length, which is because the breakdown point is transferred from the higher electric field area with the maximum curvature radius to the low electric field area. The simulated R on,sp of SiC/Si VDMOS is 17.4 mΩ•cm 2 with the BV of 578 V, which is lower than that of 41.01 mΩ•cm 2 with the BV of 226V in Si VDMOS. The silicon limit relationship has been broken for SiC/Si VDMOS.

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Section: Device Structure and Descriptionmentioning

confidence: 99%

Section: Device Structure and Descriptionmentioning

confidence: 99%

SiC/Si heterojunction VDMOS breaking silicon limit by breakdown point transfer technology

Duan

Zhao

et al. 2018

Micro & Nano Letters

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“…[9] The emergence of Si/SiC substrate makes it possible to solve the above problems. [10][11][12][13][14] A novel Si/SiC heterojunction LDMOS with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. PBL Si/SiC LDMOS takes full advantages of the Si/SiC substrate by preparing the electrodes on the epitaxial layer of Si, and the drain region of the device is deep into the SiC substrate, avoiding the reliability problems of SiC gate oxide, while also taking advantage of the high critical electric field of the SiC.…”

Section: Introductionmentioning

confidence: 99%

Novel Si/SiC heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit*

Duan¹,

Huang²,

Song³

et al. 2021

Chinese Phys. B

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A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (R on,sp). Through TCAD simulation, when the drift region length is 20 μm, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μm, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit.

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“…Moreover, manufacturing SiC devices is much more costly compared with Si devices. The successful fabrication of Si/SiC substrates offers a practical approach to solve these problems [12][13][14][15][16].…”

mentioning

confidence: 99%

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Duan

Xing

Yang

2019

Micro & Nano Letters

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A novel silicon (Si) on silicon carbide (SiC) lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region is proposed. Its main idea is transferring the breakdown point and utilising the high critical electric field of SiC material to suppress the curvature effect of the drain, which eventually alleviates the trade-off relationship between breakdown voltage (BV) and specific on-resistance (R on,sp). Through the TCAD simulation, the results show that the BV is significantly improved from 240 V for conventional Si lateral double-diffused metal oxide semiconductor (LDMOS) to 384 V for the proposed structure with the drift region length of 20 μm, increased by 60%. The figureof-merit of the conventional Si LDMOS and the Si/SiC LDMOS are 2.04 and 4.26 MW/cm 2 , respectively. It indicates that the proposed structure has better performance than the Si counterpart. The influences of design parameters and interfacial charges on the device performance are also discussed in this work.

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Drain current - gate voltage characteristics of Si MOSFETs fabricated on Si-on-SiC wafers

Cited by 7 publications

References 3 publications

SiC/Si heterojunction VDMOS breaking silicon limit by breakdown point transfer technology

SiC/Si heterojunction VDMOS breaking silicon limit by breakdown point transfer technology

Novel Si/SiC heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit*

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

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