Down-Coupling Phenomenon of Floating Channel in 3D NAND Flash Memory

Kim, Yoon; Kang, Myounggon

doi:10.1109/led.2016.2619903

Cited by 35 publications

(25 citation statements)

References 7 publications

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“…Such mismatch could be attributed to several physical mechanisms already debated in literature [10], [11], [12] related to the peculiar behavior of the poly-Si channel. Although all the tests in those works were performed either on single cells/test element groups or on TCAD simulations, we found some evident similarities especially in the transient current instabilities phenomenology.…”

Section: Discussion On the Tre Naturementioning

confidence: 97%

“…Besides those intrinsic mechanisms, there are additional reliability detractors related to the structure of the 3D-NAND cells. The use of a poly-silicon (poly-Si) material for the cells' channel and their vertical integration in relatively long pillars exposes the V T distributions to unwanted broadening and shifts [1], [8], [9], [10], [11], [12].…”

Section: Introductionmentioning

confidence: 99%

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First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Zambelli

Micheloni²,

Scommegna³

et al. 2020

IEEE J. Electron Devices Soc.

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This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent change of cell threshold voltage between the program verify and the following read operations, but to its transient instability occurring during the idle phase and the first read operations performed on a block. The experimental analysis has been performed on off-the-shelf gigabit-array products to characterize the dependence on the memory operating conditions. The TRE is found to be strongly dependent on the page read, on the read temperature and on the time delay between the first and the second read after the idle state. To emphasize its negative impact at system-level, we have evaluated the induced performance drop on Solid State Drives architectures. INDEX TERMS 3D-NAND flash, characterization, fail bits, read errors, reliability, solid-state drives (SSD).

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Section: Discussion On the Tre Naturementioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Zambelli

Micheloni²,

Scommegna³

et al. 2020

IEEE J. Electron Devices Soc.

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“…In this paper, TCAD simulation was performed to observe NLSB for each WL in 3D NAND Flash memory. The parameters were used based on the simulation data validated in the previous study, and Table 1 lists the parameters used in the TCAD simulation [7][8]. In addition, 16 WL, GSL, and SSL composed the entire 3D NAND string and the internal structure is the same as in the previous research.…”

Section: Device Parameter Valuementioning

confidence: 99%

“…The structure of 3D NAND flash memory is based on an ultra-thin body (UTB) structure in which the channel of the main cell is not connected to the body, and body bias is not applicable to the channel of the main cell. This can cause the channel to float, resulting in the down coupling phenomenon (DCP) and natural local self-boosting (NLSB) phenomena [5][6][7][8]. When program voltage (V PGM ) is applied to selected word-line (WL) of 3D NAND flash memory, program operation should not be performed on the selected WL of inhibit string.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

et al. 2020

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Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical potential boosting. In addition, in the region of the middle cells (WL6 through WL10), a slight change in the potential boosting was also almost the same. In the 3D NAND, where there was a dummy WL (DWL), the NLSB for the edge WL changed as the pattern of the DWL changed. The DWL did not affect the NLSB of the main cell, regardless of the pattern. Therefore, the high potential of the edge WL could reduce the potential difference between the main cell and the edge WL using the DWL.

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“…Various memory devices, such as static random-access memories (SRAM) [7], resistive random-access memories (RRAM) [8], phase change memories (PCM) [9], floating gate-memories (FG-memory) [10] and charge-trap flash memories [11] have been proposed to implement the synapse operation. Among them, charge-trap flash (CTF) devices have good CMOS compatibility and excellent reliability [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application

Choi

Park²,

Lee

et al. 2019

Electronics

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In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. In our previous work, we proposed the 3-D synapse array architecture based on a charge-trap flash (CTF) memory. It has the advantages of high-density integration of 3-D stacking technology and excellent reliability characteristics of mature CTF device technology. This paper examines some issues of the 3-D synapse array architecture. Also, we propose an improved structure and programming method compared to the previous work. The synaptic characteristics of the proposed method are closely examined and validated through a technology computer-aided design (TCAD) device simulation and a system-level simulation for the pattern recognition task. The proposed technology will be the promising solution for high-performance and high-reliability of neuromorphic hardware systems.

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Down-Coupling Phenomenon of Floating Channel in 3D NAND Flash Memory

Cited by 35 publications

References 7 publications

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application

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