First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Abstract

This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent change of cell threshold voltage between the program verify and the following read operations, but to its transient instability occurring during the idle phase and the first read operations performed on a block. The experimental analysis has been performed on off-the-shelf gigabit-array products to characterize the dependence on the memory operating conditions. The TRE is found to be strongly dependent on the page read, on the read temperature and on the time delay between the first and the second read after the idle state. To emphasize its negative impact at system-level, we have evaluated the induced performance drop on Solid State Drives architectures. INDEX TERMS 3D-NAND flash, characterization, fail bits, read errors, reliability, solid-state drives (SSD).

A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory

“…As mentioned above, the program suspend command can be issued at any instant, and subsequent operations may arrive after a long idle time. In addition, studies [12], [16]- [18] have shown that read FBC increases when read operations are issued after a long idle time. Therefore, the reliability of devices undergoing the program suspend operation is concerned.…”

A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories

“… ( a ) The TLC 3D NAND Flash architecture. Reprinted with permission from [ 9 ] under Creative Commons License 4.0 (CC-BY). ( b ) Sequence of operations during program operation considering on-chip randomization.…”

“…From the reliability standpoint, the 3D NAND Flash technology inherits the issues already documented for planar NAND Flash, such as wear-out failures due to repeated data writing/erasing (i.e., endurance failures [ 4 ]), high temperature sensitivity either in static (i.e., data retention [ 5 ]) or in dynamic (i.e., cross-temperature [ 6 ]) working conditions, and disturbances due to frequent access to the memory (e.g., read disturb [ 7 ]). On top of these, novel reliability threats specifically belonging to the physical nature of 3D devices come into play [ 8 , 9 ]. At the system level, all these reliability detractors are perceived through an increase of the Fail Bits Count (FBC) exposed by the 3D NAND Flash after operation.…”

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

“…The presence of grains separated by highly defective grain boundaries in the polysilicon channel of the strings introduces some relevant issues in the operation and in the reliability of the array. Among them, it is worth mentioning (i) a severe limitation to the string current, especially at low temperature [7]; (ii) transient instabilities in the string current, due to the dependence of the average occupancy of the traps at the grain boundaries on the bias history of the string [8][9][10]; (iii) variability in the cell threshold voltage ( V T ) and in its temperature dependence, due to the haphazardness in the configuration of the polysilicon grains [11,12]; (iv) the worsening of the amplitude statistics of random telegraph noise (RTN) affecting cell V T , due to the contribution to percolative channel conduction of the nonuniform inversion of the intra-grain and inter-grain regions [13][14][15][16][17][18][19]. The adoption of a thin annular channel instead of a full nanowire was demonstrated to be a successful solution to mitigate some of these issues [20,21].…”