A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory

Abstract

Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the program suspend command is issued during the program stage, and particularly, they become more obvious as the delay time between program suspend operation and other following operations exceeds tens of milliseconds. By analyzing the waveform of conventional program suspend scheme, it is suggested that the unexpected extra read fail bits are caused by the different occupancy of grain boundary traps (GBTs) in the polycrystalline silicon (poly-Si) channel during the idle time after the program suspend operation. Accordingly, a novel program suspend scheme is proposed by adding a "stabilizing" pulse immediately after the program stage. Silicon experimental data show that the proposed scheme can effectively limit the read fail bit count (FBC) to a normal range, thus improving the reliability of 3D NAND flash memory significantly.

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory

“…The arraylevel program distributions between the first read and the second read (denoted as ∆Vt) are explained in Figure 2c. A larger ∆Vt would induce a higher fail bit count during the read operation [12]; hence suppressing ∆Vt (program disturbance) can significantly ameliorate the reliability of 3D NAND flash.…”

Address Pattern Recognition Flash Translation Layer for Quadruple-level cell NAND-based Smart Devices

“…As a result, instead of applying high-performing single-level cell (SLC) or multi-level cell (MLC) technology to smart devices, major semiconductor companies are developing QLC flash memory for smart devices. However, implementing QLC flash memories on smart devices may drastically diminish device performance and durability and even generate inconsistent response times, as smart devices must generate frequent updates from temporary files and metadata [3]. Furthermore, smart devices may execute unnecessary write operations on QLC-based SSDs because of the large page size of QLC flash memory.…”