Double Node Upset Tolerant RHBD15T SRAM Cell Design for Space Applications

Raghuram, Naga; Gupta, Bharat; Kaushal, Gaurav

doi:10.1109/tdmr.2020.2970089

Cited by 21 publications

(9 citation statements)

References 42 publications

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“…Two 18T and 24T cells are proposed in [32] that provide complete tolerance against SEUs but at the cost of considerable area overhead. Similarly, the cells proposed in [33] and [34] have high area overhead making them less suitable for cache designs.…”

Section: ) Previous Cell Designs That Provide Seu Tolerance But Have ...mentioning

confidence: 99%

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy efficiency, reliability is a main issue since the system is launched into space with a limited energy budget and stay exposed to high doses of radiation strikes for a long time. The Nwise cell has recently been proposed by the authors of this paper as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI. In this paper, inspired from the Nwise cell, we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell, which is also designed with 28nm FD-SOI technology. Through comprehensive simulations of state-of-the-art cells, we show that both the Nwise and Pwise cells are competitive radiation hardened SRAMs to use in different memory blocks for space applications: (1) Both have the highest level of Single Event Upsets (SEU) tolerance capability for the temperature range deployed in space applications; further, both have the highest level of the tolerance capability to Multi Event Upsets (MEU). ( 2) Compared with the simulated cells that have comparable tolerance capability, the Nwise cell has low read delay and read power consumption, hence, it can be a good choice for space application cache designs, while the Pwise cell can be a proper candidate for space application register file designs since it has low write and read delay.

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Section: ) Previous Cell Designs That Provide Seu Tolerance But Have ...mentioning

confidence: 99%

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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“…For this issue, many authors proposed various circuits to tolerate both SEU and SEMNU. Under these category RHD‐12T, 36 RSP‐ 14T, 55 RHBD‐15T, 56 RHPD‐12T, 57 SAR‐14T, 58 SRRD‐12T, 59 RHMD‐10T, 60 SEA‐14T, 61 DA‐12T, 62 RH‐14T, 63 SIRI‐14T, 64 HP‐12T, 65 and RHAE‐10T 66 are the circuits which tolerate SEU and SEMNU partially. And each has its own constraints.…”

Section: Review Of Various Radiation‐hardened Approachesmentioning

confidence: 99%

“…Another robust approach to mitigate radiation problems is RHBD‐15T, as shown in Figure 15H. In this design, 56 author Naga Raghuram et al considered four primary storage nodes q, qn, s0, and s1, and four redundant nodes x, y and w, z are the replica nodes of q and qb, respectively. Additionally, the author separated the read bit line from the main bit line to improve the RAT.…”

Section: Review Of State Of Art Rhbd Sram Cellsmentioning

confidence: 99%

A review on radiation‐hardened memory cells for space and terrestrial applications

Mukku¹,

Lorenzo²

2022

Circuit Theory & Apps

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Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area.Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of Q Crit and the impact of Q Crit on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells.critical charge, figure of metric, single event upset, single event multiple node upset, soft error | INTRODUCTIONTo enhance the functionality of system-on-chip (SoC), designers scale down the dimensions of the transistors. 1 According to the international technology roadmap for semiconductors (ITRS) prediction on memory size, and its processing engines on mobile type SoC, it is expected to rise by a factor of 18 between 2013 and 2025, 2,3 which is shown in Figure 1. Massive increasing the transistor count certainly increases the power consumption and degrade the mobile battery's life.Recent SoCs are embedded with static random access memory (SRAM) memories due to the faster and more reliable read/write approaches. Therefore, these SRAMs are used as cache and main memories. Moreover, SRAM memories occupy a maximum area on SoC's. 2 Hence, chip designers scale down the process technology of the memories. The problem with process technology scaling would lower the standard operating voltage, conversely, due to the process variations, memory density increases. 4 Figure 2 shows the trends of industrial standard processors and SRAM memories with various operating voltages at different technology nodes presented in ISSCC. 3 Scaling the process technology node of SRAM memories is more sensitive to transistor variations. 5 This scaling also increases the soft error rate (SER). Ibe et al 6 discuss the SER of SRAM memories in 22 nm node rises by a factor of 7 as compared with 130 nm design. On the other hand, when an electronic component is subjected to radiation, its electrical properties change due to technology node scaling, large densities, and lower operating voltages. These exposures to radiation cause temporary or permanent system breakdown.Three distinct radiation environments are feasible to define, from earth's sea level to the planet's space orbit. They are terrestrial, atmospheric, and van Allen belt radiations. The National Aeronautical Space Administration (NASA) investigated spacecraft anomalies between 1974 and 1994 space missions. 7 Among those 100 various missions, it is clear that 35% and above of anomalies are caused to spacecraft failure due to the electronic component's radiation effects. So

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“…3 At the layout level, source-isolation technology, 8 source-expansion technology, 9 T-gates, 10 H-gates, 10 and other techniques can alleviate the problem of radiation influence on the cell to a certain extent, but it will reduce robustness and lead to satisfy more complex layout rules. 11 In recent years, radiation-hardened of SRAM cell circuit by design has become the mainstream technology. Its principle is to combine circuit structure and layout structure and use circuit feedback loop to realize data recovery of storage nodes.…”

Section: Introductionmentioning

confidence: 99%

“…At the process level, the SOI process can reinforce cell stability, but the production cost in this process is high, preventing its use on a large scale 3 . At the layout level, source‐isolation technology, 8 source‐expansion technology, 9 T‐gates, 10 H‐gates, 10 and other techniques can alleviate the problem of radiation influence on the cell to a certain extent, but it will reduce robustness and lead to satisfy more complex layout rules 11 …”

Section: Introductionmentioning

confidence: 99%

Write‐enhanced and radiation‐hardened SRAM for multi‐node upset tolerance in space‐radiation environments

Zhao

Dong

Peng

et al. 2022

Circuit Theory & Apps

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Summary As transistor feature size is scaling down, the probability of charge sharing in a space‐radiation environment increases because of the reduced distance between adjacent transistors. The single‐event multiple‐node upset (SEMNU) caused by charge sharing is a major source of data errors in high‐density static random‐access memory (SRAM). In this paper, a radiation‐hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD‐12T, RSP14T, SEA14T, We‐Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC‐14T cell saves 8.47%, 91.34%, 162.71%, ‐20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read‐delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write‐delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation‐intensive space environment.

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Double Node Upset Tolerant RHBD15T SRAM Cell Design for Space Applications

Cited by 21 publications

References 42 publications

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

A review on radiation‐hardened memory cells for space and terrestrial applications

Write‐enhanced and radiation‐hardened SRAM for multi‐node upset tolerance in space‐radiation environments

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