Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Kim, Keunwoo; Fossum, J.G.

doi:10.1109/16.902730

Cited by 162 publications

(18 citation statements)

References 11 publications

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“…Based on specific physics in the bottom gate‐controlled LTPS TFT described in Figures 1 and 2, the bottom‐gate voltage can be physically derived as:

V_{GbS} ≅ V_{FBb} goodbreak- \frac{C_{italicpSi}}{C_{italicbox}} \cdot ψ_{sf} goodbreak+ ((), 1 goodbreak+ \frac{C_{italicpSi}}{C_{italicbox}}) \cdot ψ_{sb} goodbreak- \frac{Q_{italiccb}}{C_{italicbox}} goodbreak- \frac{Q_{italicpSi}}{2 C_{box}}

where V GbS is the bottom gate‐to‐source voltage, V FBb is the bottom‐gate flat‐band voltages, ψ sf and ψ sb are the front and back surface potentials, Q cb is the back‐surface charge density, Q pSi is the depletion charge in the polysilicon expressed as Q pSi

≅

‐qN A T pSi where T pSi is the polysilicon thickness, C GI and C box are the front‐ and back‐gate oxide capacitances, and C pSi

true(≅

ε pSi /T pSi ) is the depletion capacitance 5,17 . In the same way as (), the front‐gate voltage ( V GfS ) can be derived as:

V_{GfS} ≅ V_{FBf} goodbreak+ ((), 1 goodbreak+ \frac{C_{italicpSi}}{C_{italicGI}}) \cdot ψ_{sf} goodbreak- \frac{C_{italicpSi}}{C_{italicGI}} \cdot ψ_{sb} goodbreak- \frac{Q_{italiccf}}{C_{italicGI}} goodbreak- \frac{Q_{italicpSi}}{2 C_{GI}}

where V GfS is the (front) gate‐to‐source voltages, V FBf is the front‐gate flat‐band voltages, ψ sf and ψ sb are the front and back surface potentials, and Q cf is the front‐surface charge densities.…”

Section: Bottom‐gate Ltps Tft Technologiesmentioning

confidence: 99%

“…where V GbS is the bottom gate-to-source voltage, V FBb is the bottom-gate flat-band voltages, ψ sf and ψ sb are the front and back surface potentials, Q cb is the back-surface charge density, Q pSi is the depletion charge in the polysilicon expressed as Q pSi ffi -qN A T pSi where T pSi is the polysilicon thickness, C GI and C box are the front-and backgate oxide capacitances, and C pSi ffi ð ε pSi /T pSi ) is the depletion capacitance. 5,17 In the same way as (1), the front-gate voltage (V GfS ) can be derived as: where V GfS is the (front) gate-to-source voltages, V FBf is the front-gate flat-band voltages, ψ sf and ψ sb are the front and back surface potentials, and Q cf is the front-surface charge densities. In the accumulation charge condition for p-channel LTPS TFTs, the surface potential or band bending reach a constant potential near the Fermi level.…”

Section: Bottom-gate Ltps Tft Technologiesmentioning

confidence: 99%

“…In Figure 3B, the extracted data for V th vs. V bottom from the results of Figure 3A is shown. It is demonstrated that back gatecontrolled LTPS TFTs can offer a wide-tunable range V th by adjusting V bottom as well as depositing the structural CVD layers in (5). The back gate electrically modulates the predominant front channel current via a gate-to-gate coupling.…”

Section: Bottom-gate Ltps Tft Technologiesmentioning

confidence: 99%

“…In first‐principle physics, the double‐gate field‐effect transistors appear more electrostatic than the single‐gate counterparts due to the electrical coupling of two gates 4,5 . This fundamental benefit can be applied to low‐temperature polysilicon (LTPS) thin‐film transistor (TFT) structures in display applications using optimal bottom gate‐controlled device structures 6 .…”

Section: Introductionmentioning

confidence: 99%

“…3 In first-principle physics, the double-gate field-effect transistors appear more electrostatic than the single-gate counterparts due to the electrical coupling of two gates. 4,5 This fundamental benefit can be applied to lowtemperature polysilicon (LTPS) thin-film transistor (TFT) structures in display applications using optimal bottom gate-controlled device structures. 6 As recently reported, bottom gate-aided LTPS TFTs can potentially offer better image quality and recoverable residual image sticking, especially in flexible displays due to shielding the electric fields from polyimide charging effects.…”

Section: Introductionmentioning

confidence: 99%

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Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

et al. 2023

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This paper presents a recent process for bottom gate-controlled lowtemperature polysilicon (LTPS) TFT technologies for reliable low-power highperformance AMOLED displays. The experimental and physics-based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. The process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates-based device structures, is explored in conjunction with improved poly crystallization and poly-Si/gateoxide interface by reducing defect density-of-state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance, such as optimal sub-threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics-based analysis, are performed to corroborate experimental results in fabricated TFTs and gain more physical insight into the bottom-gate LTPS device configuration to enable reliable low-power high-performance AMOLED display applications.bottom gate, density-of-state (DOS), drain-induced barrier lowering (DIBL), drive current (Ion), grain boundary, hot carrier injection (HCI), leakage current (Ioff), low-temperature polysilicon (LTPS) TFTs, negative bias temperature instability (NBTI), plasma-enhanced chemical vapor deposition (PECVD), short-channel effects (SCEs)

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“…Based on specific physics in the bottom gate‐controlled LTPS TFT described in Figures 1 and 2, the bottom‐gate voltage can be physically derived as:

V_{GbS} ≅ V_{FBb} goodbreak- \frac{C_{italicpSi}}{C_{italicbox}} \cdot ψ_{sf} goodbreak+ ((), 1 goodbreak+ \frac{C_{italicpSi}}{C_{italicbox}}) \cdot ψ_{sb} goodbreak- \frac{Q_{italiccb}}{C_{italicbox}} goodbreak- \frac{Q_{italicpSi}}{2 C_{box}}

≅

‐qN A T pSi where T pSi is the polysilicon thickness, C GI and C box are the front‐ and back‐gate oxide capacitances, and C pSi

true(≅

ε pSi /T pSi ) is the depletion capacitance 5,17 . In the same way as (), the front‐gate voltage ( V GfS ) can be derived as:

V_{GfS} ≅ V_{FBf} goodbreak+ ((), 1 goodbreak+ \frac{C_{italicpSi}}{C_{italicGI}}) \cdot ψ_{sf} goodbreak- \frac{C_{italicpSi}}{C_{italicGI}} \cdot ψ_{sb} goodbreak- \frac{Q_{italiccf}}{C_{italicGI}} goodbreak- \frac{Q_{italicpSi}}{2 C_{GI}}

Section: Bottom‐gate Ltps Tft Technologiesmentioning

confidence: 99%

Section: Bottom-gate Ltps Tft Technologiesmentioning

confidence: 99%

Section: Bottom-gate Ltps Tft Technologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

et al. 2023

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show abstract

40‐3: Distinguished Paper: Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

Kim,

Sung,

Kim

et al. 2023

Symp Digest of Tech Papers

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This paper presents recent process for bottom gate‐controlled low‐temperature polysilicon (LTPS) TFT technologies for reliable low‐power high‐performance AMOLED displays. Experimental and physics‐based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. Process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates‐based device structures, is explored in conjunction of improved poly crystallization and poly‐Si/gate‐oxide interface by reducing defect density‐of‐state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance such as optimal sub‐threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate experimental results in fabricated TFTs, as well as gain more physical insight in the bottom‐gate LTPS device configuration, to enable reliable low‐power high‐performance AMOLED display applications.

show abstract

Mobility in Multigate MOSFETs

Gámiz

Godoy

FinFETs and Other Multi-Gate Transistors

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Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Cited by 162 publications

References 11 publications

Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

40‐3: Distinguished Paper: Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

Mobility in Multigate MOSFETs

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