This paper presents recent progress to scale down low‐temperature polysilicon (LTPS) TFT technologies in the extremely short‐channel length regime for AMOLED displays. Process integration of short‐channel gate and narrow‐width polysilicon into scaled equivalent gate‐oxide thickness (EOT), is explored, in conjunction with enhanced poly crystallization by reducing defect density‐of‐state (DOS) especially in the grain boundaries of the channel region. We obtain more than twice higher current drive (Ion) with significantly‐reduced parasitic gate capacitance, thereby enabling high‐performance high‐frequency panel operations. In addition to superior panel performance in scaled LTPS TFTs, reliable devices are attained, demonstrating robust device characteristics for negative‐bias instability (NBTI) and hot carrier injection (HCI) effects. Physics‐based analysis, based on experimental data and numerical device simulations, is performed to gain more insight in the TFT technologies.

This paper presents extremely‐low leakage technologies in low‐temperature polysilicon (LTPS) TFTs. Experimental and physics‐based analysis of leakage currents, emphasizing the effects of process technologies and device design, are described. Small‐geometry TFTs, controlled by optimal LTPS process, dramatically reduce off‐state leakage current (Ioff) by suppressing gate‐induced drain leakage (GIDL) and thermal generation currents, thus potentially offering lower frame rate operations by reducing IC clock power. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate the remarkable low‐Ioff experimental results as well as more‐than‐twice enhanced on‐state current (Ion) in optimized LTPS devices.

This paper presents a recent process for bottom gate-controlled lowtemperature polysilicon (LTPS) TFT technologies for reliable low-power highperformance AMOLED displays. The experimental and physics-based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. The process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates-based device structures, is explored in conjunction with improved poly crystallization and poly-Si/gateoxide interface by reducing defect density-of-state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance, such as optimal sub-threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics-based analysis, are performed to corroborate experimental results in fabricated TFTs and gain more physical insight into the bottom-gate LTPS device configuration to enable reliable low-power high-performance AMOLED display applications.bottom gate, density-of-state (DOS), drain-induced barrier lowering (DIBL), drive current (Ion), grain boundary, hot carrier injection (HCI), leakage current (Ioff), low-temperature polysilicon (LTPS) TFTs, negative bias temperature instability (NBTI), plasma-enhanced chemical vapor deposition (PECVD), short-channel effects (SCEs)