Double edge triggered feedback flip-flop in sub 100nm technology

Rasouli,; Amirabadi,; Seyedi,; Afzali-Kusha,

doi:10.1109/aspdac.2006.1594698

Cited by 5 publications

(3 citation statements)

References 11 publications

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“…Most implementations of them are based on the combinational logic to avoid the speed degradation of feedback delay even in case of PRBS (Pseudo-Random Bit Sequence) [1] or LFSR (Linear Feedback Shift Registers) [6] generator which are typical applications of the logic with XOR feedback. Although there are some papers deal with the ultrahigh-speed logic with feedback [7][8][9], they focus only on the divider which output signal is directly fed back to the input terminal. In other words, they are the special case of the logic with feedback because there is no any delay in the feedback path.…”

Section: Introductionmentioning

confidence: 99%

10-Gb/s CMOS ultrahigh-speed gold-code generator using differential-switches feedback

Wang

Juang

et al. 2007

2007 European Microwave Integrated Circuit Conference

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This paper proposes a new architecture for the implementation of an n-input XOR gate in ultrahigh-speed applications. The new circuitry makes it possible to let the conventional sequence logic with XOR feedback, such as Gold code generator, to work up to ten-gigabit per second. This paper will systematically describe the principle of substituting a set of differential switches for an XOR gate. The proposed circuitry is demonstrated in a five-stage Gold code generator implemented in TSMC 0.18-µm 1P6M CMOS process. The simulation results show that the delay of the proposed four-input XOR gate is so much improved as to let the five-stage (5,3) and (5,4,3,2) Gold code generator to work up to 10 Gb/s. Index Terms -CMOS, differential switch, Gold-code generator, high-speed XOR.

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Section: Introductionmentioning

confidence: 99%

10-Gb/s CMOS ultrahigh-speed gold-code generator using differential-switches feedback

Wang

Juang

et al. 2007

2007 European Microwave Integrated Circuit Conference

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“…Charging (discharging) internal node X2 (X1) is done through three transistors that incur reduction of the circuit speed. To avoid unnecessary transitions in previous logic, [10] is proposed Doubleedge triggered Feedbacked Flip-Flop (DFFF) whose circuit is shown in Fig. 4.…”

Section: Double-edge Triggered Flip-flopsmentioning

confidence: 99%

“…Furthermore, number of transistors in this logic is much greater than previous works. Double-edge triggered Feedbacked Flip-Flop (DFFF) has been proposed in Bulk technology in [10] that has lower number of transistors as well as less power consumption and delay compared to the previous flipflops. Furthermore, the leakage power is very low in these flip-flops compared to the others.…”

Section: Introductionmentioning

confidence: 99%

Comparing The Performance Of A Low-power High Speed Flip-flop In Bulk And Soi Technologies

Forouzandeh

Seyedi

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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In this paper, the performance of Double-edge triggered Feedbacked Flip-Flop (DFFF) in SOI and Bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to less delay and thus higher operational speed compared to the other flip-flops. By using SOI technology, the power consumption and speed have been improved further compared to Bulk technology. The performance improvement is 37.10% to 45.54% for discussed flip-flops compared to Bulk technology.

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