Comparing The Performance Of A Low-power High Speed Flip-flop In Bulk And Soi Technologies

Abstract

In this paper, the performance of Double-edge triggered Feedbacked Flip-Flop (DFFF) in SOI and Bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to less delay and thus higher operational speed compared to the other flip-flops. By using SOI technology, the power consumption and speed have been improved further compared to Bulk technology. The performance improvement is 37.10% to 45.54% for discussed flip-flops compared to Bulk technology.

10-Gb/s CMOS ultrahigh-speed gold-code generator using differential-switches feedback

“…Most implementations of them are based on the combinational logic to avoid the speed degradation of feedback delay even in case of PRBS (Pseudo-Random Bit Sequence) [1] or LFSR (Linear Feedback Shift Registers) [6] generator which are typical applications of the logic with XOR feedback. Although there are some papers deal with the ultrahigh-speed logic with feedback [7][8][9], they focus only on the divider which output signal is directly fed back to the input terminal. In other words, they are the special case of the logic with feedback because there is no any delay in the feedback path.…”