10-Gb/s CMOS ultrahigh-speed gold-code generator using differential-switches feedback

Lu, Chun-Lin; Wang, H.-C.; Juang, Jyh‐Ching; Chuang, Huey-Ru

doi:10.1109/emicc.2007.4412693

Cited by 3 publications

(2 citation statements)

References 12 publications

(15 reference statements)

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“…Gold sequences are a set of specific sequences found in systems employing a spread spectrum or code division multiple access (CDMA) techniques. These systems are often used in communications equipment, such as cellular phones, GPS devices, and very small aperture satellite terminals (VSATS) [20]- [22]. Figure 3 shows the structure of the existing gold sequence generator with degree N. The gold sequence d(n) belongs to a family of codes with well-behaved cross-correlation properties that are constructed using a modulo-2 addition of the specific relative phases of a preferred pair of pseudorandom sequences, x 0 (n) and x 1 (n) [23].…”

Section: Application Examplementioning

confidence: 99%

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

Hwang¹

2010

ETRI J

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A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a 2×2 multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.Keywords: pseudorandom sequence generator, linear feedback shift register, matrix multiplication, 3GPP LTE system, MIMO detector. Manuscript received Sept. 4, 2009; revised Dec. 17, 2009; accepted Jan. 4, 2010. This work was supported by the IT R&D program of MKE/KEIT, Rep. of Korea [2006-S-001-04 I. IntroductionPseudorandom sequences [1] have been widely used in various fields, including communications, navigation, radar technology, cipher technologies, remote control, measurements, and industrial automation [2]. For example, pseudorandom sequences have been used in error-correcting codes [3], spread spectrum communication [4], [5], and system identification and parameter measurements [6], [7]. Other example applications are found in surface characterization and 3D scene modeling [8]. The design of a general purpose pseudorandom sequence generator has matured and has already been commercialized [9]-[11].Pseudorandom sequences are series of 1's and 0's that lack any definite pattern and look statistically independent and uniformly distributed. The sequences are deterministic, but exhibit noise properties similar to randomness [12]. In particular, a pseudorandom sequence generator is usually made up of shift registers with feedback. By linearly combining elements from taps of the shift register and feeding them back to the input of the generator, we can obtain a sequence of much longer repeat length using the same number of delay elements in the shift register. Therefore, these blocks are also referred to as a linear feedback shift register (LFSR) [13], [14]. The length of the shift register, the number of taps, and their positions in the LFSR are important to generate pseudorandom sequences with desirable auto-correlation properties [15]. However, the output of the conventional pseudorandom sequence generator is limited to 1 bit per clock cycle. This restriction can be a bottleneck for data communications and may cause a delay. have been proposed [16], [17]. The approaches describe a parallel architecture implementation of a pseudorandom...

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Section: Application Examplementioning

confidence: 99%

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

Hwang¹

2010

ETRI J

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“…It consists of a voltage-controlled oscillator (VCO) [17,18], an RC phase splitter, a frequency doubler, and a phase modulator implemented in 0.13-µm CMOS technology. The differential switch pair [19], a component in the double-balanced mixer, is used to multiply the LO signal and the RF signal to achieve very high frequencies.…”

Section: Introductionmentioning

confidence: 99%

A K-BAND TRANSMITTER FRONT-END BASED ON DIFFERENTIAL SWITCHES IN 0.13-µm CMOS TECHNOLOGY

Wang

Juang²,

2011

PIER C

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This paper presents the design and test results of a 20-GHz transmitter front-end implemented in the TSMC 0.13-µm CMOS process. The chip consists of a voltage-controlled oscillator (VCO), an RC phase splitter, and two differential switches. To realize the K-band transmitter function, the two different switches are designed to serve the purpose of frequency doubler and phase modulator, respectively. These two features are verified in the implemented chip and, as a result, the chip can serve as a transmitter front-end. The measured total current consumption of the chip core circuit is 26 mA under a DC supply voltage of 1.2 V. The chip size is 1.03 × 0.93 mm 2 .

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Design of a 24-GHz PSK transmitter for SRR applications based on differential switches in 0.13-um CMOS process

Wang

Hsu

Juang

et al. 2009

2009 Asia Pacific Microwave Conference

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10-Gb/s CMOS ultrahigh-speed gold-code generator using differential-switches feedback

Cited by 3 publications

References 12 publications

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

A K-BAND TRANSMITTER FRONT-END BASED ON DIFFERENTIAL SWITCHES IN 0.13-µm CMOS TECHNOLOGY

Design of a 24-GHz PSK transmitter for SRR applications based on differential switches in 0.13-um CMOS process

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