Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

Lahgere, Avinash; Panchore, Meena; Singh, Jawar

doi:10.1016/j.spmi.2016.05.004

Cited by 37 publications

(9 citation statements)

References 21 publications

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“…The NOR logic operation is non-sustainable for up to 1,000 bending cycles with wide transition width of ~0.26 V is the main drawback. Lahgere et al [15] have proposed a TFET based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep sub threshold swing. The dopingless silicon nanowire used with CP has a genuine advantage in the process of both technology boosters and it enables the low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with counterpart dopingless (DL) TFET (DL-TFET).…”

Section: Related Workmentioning

confidence: 99%

Low Power Strain and Dimension Aware SRAM Cell Design Using a New Tunnel FET and Domino Independent Logic

Reddy¹,

Jayasree²

2018

IJIES

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Mechanical strain and dimension in silicon leads to band splitting and alters the effective mass which results in carrier mobility changes. Induced strain and dimension effects on channel can be either "tensile" or "compressive". NMOS and PMOS devices have different desired strain and dimension types in the longitudinal, lateral and Si-depth dimensions. The small band gap tensile strained silicon is more compatible than conventional silicon processing for low power circuit design. In this paper, we propose strain and dimension aware circuit (SDAC) design using new physics model and domino clock and input dependent (d-INDEP) logic. In SDAC design, an optimal depleted strained TFET physics model is used to improve the on-current and steep sub-threshold swing, which are main cause of strain and dimension effects. The performance of any logic design is reduced by increasing leakage current and variability of parameters, which affects the power consumption problem. The problem is overcome by the d-INDEP logic that reduces leakage current as well as affected power without extra logics. The proposed physics and low power logic is tested with SRAM cell and simulated in HSPICE tool. The simulation result shows the effectiveness of proposed SDAC design in terms of power and delay.

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Section: Related Workmentioning

confidence: 99%

Low Power Strain and Dimension Aware SRAM Cell Design Using a New Tunnel FET and Domino Independent Logic

Reddy¹,

Jayasree²

2018

IJIES

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“…Researchers have proposed the DLTFETs and the Junction-less tunneling field effect transistors (JLTFETs) to overcome the problems of lower on-state current, larger miller capacitance, and the heavily doped steep junction [19]. The JLTFETs and DLTFETs can improve the device performance by rationally designing the electrode work function to decrease the tunneling barrier width, so the that both devices can obtain the advantages of ultra-low sub-threshold swing (SS) and off-state leakage current.…”

Section: Introductionmentioning

confidence: 99%

TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

et al. 2020

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The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

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“…A DLTFET can form heavily doped source and drain regions using the appropriate metal electrode work functions. Due to the absence of an abrupt junction, the fabrication processes of DLTFETs are simpler, and random doping fluctuations have no effect on device performance [20][21][22]. Therefore, it is possible to produce DLTFET devices more innovatively with the development of fabrication processes, such as the etching process, epitaxial growth process, and atomic layer deposition (ALD) process.…”

Section: Introductionmentioning

confidence: 99%

A Doping-Less Tunnel Field-Effect Transistor with Si0.6Ge0.4 Heterojunction for the Improvement of the On–Off Current Ratio and Analog/RF Performance

et al. 2019

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In this paper, a novel doping-less tunneling field-effect transistor with Si0.6Ge0.4 heterojunction (H-DLTFET) is proposed using TCAD simulation. Unlike conventional doping-less tunneling field-effect transistors (DLTFETs), in H-DLTFETs, germanium and Si0.6Ge0.4 are used as source and channel materials, respectively, to provide higher carrier mobility and smaller tunneling barrier width. The energy band and charge carrier tunneling efficiency of the tunneling junction become steeper and higher as a result of the Si0.6Ge0.4 heterojunction. In addition, the effects of the source work function, gate oxide dielectric thickness, and germanium content on the performance of the H-DLTFET are analyzed systematically, and the below optimal device parameters are obtained. The simulation results show that the performance parameters of the H-DLTFET, such as the on-state current, on/off current ratio, output current, subthreshold swing, total gate capacitance, cutoff frequency, and gain bandwidth (GBW) product when Vd = 1 V and Vg = 2 V, are better than those of conventional silicon-based DLTFETs. Therefore, the H-DLTFET has better potential for use in ultra-low power devices.

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Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

Cited by 37 publications

References 21 publications

Low Power Strain and Dimension Aware SRAM Cell Design Using a New Tunnel FET and Domino Independent Logic

Low Power Strain and Dimension Aware SRAM Cell Design Using a New Tunnel FET and Domino Independent Logic

TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

A Doping-Less Tunnel Field-Effect Transistor with Si0.6Ge0.4 Heterojunction for the Improvement of the On–Off Current Ratio and Analog/RF Performance

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