Dopant loss of ultrashallow junction by wet chemical cleaning

Abstract

Articles you may be interested inComparison of two surface preparations used in the homoepitaxial growth of silicon films by plasma enhanced chemical vapor deposition J. Vac. Sci. Technol. B 21, 970 (2003); 10.1116/1.1568352 Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures J. Appl. Phys. 93, 3545 (2003); 10.1063/1.1542916Two-dimensional dopant concentration profiles from ultrashallow junction metal-oxide-semiconductor field-effect transistors using the etch/transmission electron microscopy methodThe loss of the dopant in ultrashallow junction ͑USJ͒ by RCA standard clean ͑SC1͒ prior to the formation of side-wall spacer is quantified by using transmission electron microscopy ͑TEM͒, secondary ion mass spectroscopy, four-point probe, and source/drain extension ͑SDE͒ sheet-resistance test structure ͑SSTS͒. From the cross-sectional TEM images, the etched depth by one SC1 for n ͑p͒-type SDE was measured to be 1.5 nm ͑0.2 nm͒. From the secondary ion mass spectroscopy profiles, most of the n-type dopant implanted with arsenic at 2 keV is expected to be etched-out by four times of SC1 cleaning, while the p-type dopants are immune to SC1 cleaning. We quantified the dopant loss from sheet resistance measurements with the four-point probe and the SSTS. The effect of SC1 cleaning on transistor performance is discussed in terms of on-state current. The dopant loss by SC1 is found to be the most significant factor in process optimization for n-type field effect transistor with USJ.

Shortening of Plasma Strip Process Resulting in Better Removal of Photo Resist after High Dose Implantation

“…This makes PPS not a blanket solution for all PR stripping applications. Its reduced plasma exposure suggests application of PPS for PR stripping after sensitive implants like ultra shallow junctions [5].…”

Characterization of Oxidation Induced Substrate Loss

“…Although there is some interest in wet-only processing, the challenges related to resist and residue removal prevent this approach in the main stream and dry-only or dry-wet combinations are typically employed. Limitations are placed on plasma chemistries, driven by the need for near-zero substrate and dopant loss [1]. Continuing high-dose (>2E15), but shallow implants of multiple species, combine to make dry photoresist strip a significant challenge [2].…”

Effect of Ashing, Strip and Annealing Process on the Dopant Concentration of Silicon

“…There are several reports on dopant loss affected by the cleaning. Previous studies showed that dopant loss is occurred by wet etching in the case of ultrashallow junction (1,2,3). Using of SC1 multiple times etches the polysilicon containing dopant.…”