Domino logic designs for high-performance and leakage-tolerant applications

Moradi, Farshad; Cao, Tuan Vu; Vatajelu, Elena Ioana; Peiravi, Ali; Mahmoodi, Hamid; Wisland, Dag T.

doi:10.1016/j.vlsi.2012.04.005

Cited by 59 publications

(61 citation statements)

References 20 publications

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“…[25][26][27] The robustness of the circuit is enhanced due to the insertion of keeper transistor MP 2 with increase in the propagation delay and the power consumption. 29 For wide Fan-in gates, the robustness of FDL decreases due to a large number of interconnects. The contention between PDN and keeper increases with the increase in the size of the keeper which, in turn, increases power consumption and delay of the circuit.…”

Section: Domino Circuitsmentioning

confidence: 99%

“…The contention between PDN and keeper increases with the increase in the size of the keeper which, in turn, increases power consumption and delay of the circuit. 29,30 A current mirror transistor NM 3 is connected in parallel for reducing delay. 28 A footer n-channel CNFET is connected between the evaluation network and ground, due to that leakage current in FLDL circuit is decreases.…”

Section: Domino Circuitsmentioning

confidence: 99%

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A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adderdesigned using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder. K E Y W O R D SCNFET, Domino, Dynamic, FOM, VLSI

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Section: Domino Circuitsmentioning

confidence: 99%

Section: Domino Circuitsmentioning

confidence: 99%

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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“…Short Channel Devices (SCD)) becoming a dominating part of total power dissipation in CMOS circuit. To reduce dynamic power dissipation it is necessary to reduce the supply voltage of the circuit, reduction of supply voltage after a certain limit affects the performance of the circuit [1][2], to maintain circuit performance of the circuit it is necessary to decrease the threshold voltage as well, but it leads to leakage power dissipation. Leakage power can be reduced by increasing the threshold voltage [3].…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of Various Domino Logic Circuits for Improvement of Power and Delay Calculation

Shrivastava¹,

Rawat²

2017

IJCA

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The urge of high performance and dynamic functionalities in an integrated circuit has led to aggressive technology scaling over the years. The supply voltage (V DD ), device threshold voltage (V th ) and the device geometry are expected to be scaled further with this trend. Which results in reducing the short channel effects and increased transistor OFF-state current (I OFF ). Additionally leakage currents, higher operating frequency and on die transistor count will lead to increase in total power dissipation. Dynamic logic technique is preferred over static logic technique for the higher performance circuit due to lesser delay which enhances the speed of the circuit and overall capacitance is low compare to CMOS which reduces the power consumption. In this paper we have calculate the Average power consumption and delay of various domino circuits provided with 8 input OR gate, comparison of power, delay, and Unit Noise Gain (UNG) of different topologies. The simulation is performed in HSPICE at 65nm and 45nm process technology with supply voltage 1V and 0.9V and operating temperature of 27⁰ C at 100 MHz for fair comparison of results. We have also calculated the power consumption and delay with the variation of keeper ratio in all the existing technique at 65nm and 45nm process technology.

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“…Dynamic logics such as domino logic are widely used in many applications due to their potential advantages over static logics, especially in the high-speed data paths [1,2]. The main advantage of the dynamic logic includes its high speed and small chip area.…”

Section: Introductionmentioning

confidence: 99%

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Asyaei

2015

Integration, the VLSI Journal

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Domino logic designs for high-performance and leakage-tolerant applications

Cited by 59 publications

References 20 publications

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Comparative Analysis of Various Domino Logic Circuits for Improvement of Power and Delay Calculation

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

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