DMAPS: a fully depleted monolithic active pixel sensor—analog performance characterization

Havránek, M.; Hemperek, T.; Krüger, H.; Fu, Y.; Germic, L.; Kishishita, Tetsuichi; Mariñas, C.; Obermann, T.; Wermes, N.

doi:10.1088/1748-0221/10/02/p02013

Cited by 21 publications

(22 citation statements)

References 14 publications

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“…In [11] it was shown that depleted active pixel sensors can be made in a commercial HV CMOS technology which allows application of higher bias voltages resulting in larger depleted depths and therefore significant charge collection from drift of charge carriers which is necessary for HL-LHC environment. This was followed by several other developments in various flavours of CMOS processes resulting in prototypes of active pixel detectors with significant depleted thickness [12][13][14] which can be commonly named as depleted CMOS pixels [15]. Recent irradiation study of depleted CMOS pixels irradiated with reactor neutrons up to HL-LHC fluence was published in [16].…”

Section: Introductionmentioning

confidence: 99%

Neutron irradiation test of depleted CMOS pixel detector prototypes

et al. 2017

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Charge collection properties of depleted CMOS pixel detector prototypes produced on p-type substrate of 2 kΩcm initial resistivity (by LFoundry 150 nm process) were studied using Edge-TCT method before and after neutron irradiation. The test structures were produced for investigation of CMOS technology in tracking detectors for experiments at HL-LHC upgrade. Measurements were made with passive detector structures in which current pulses induced on charge collecting electrodes could be directly observed. Thickness of depleted layer was estimated and studied as function of neutron irradiation fluence. An increase of depletion thickness was observed after first two irradiation steps to 1·10 13 n/cm 2 and 5·10 13 n/cm 2 and attributed to initial acceptor removal. At higher fluences the depletion thickness at given voltage decreases with increasing fluence because of radiation induced defects contributing to the effective space charge concentration. The behaviour is consistent with that of high resistivity silicon used for standard particle detectors. The measured thickness of the depleted layer after irradiation with 1·10 15 n/cm 2 is more than 50 µm at 100 V bias. This is sufficient to guarantee satisfactory signal/noise performance on outer layers of pixel trackers in HL-LHC experiments.

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Section: Introductionmentioning

confidence: 99%

Neutron irradiation test of depleted CMOS pixel detector prototypes

et al. 2017

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“…To reduce the fall time, the switched reset flavour was developed. Switched reset pixels have been explored in previous works, but the reset frequency was limited to the speed of the clock signal that is used to control the switched feedback current [14]. The outputs of the CSA and of the comparator of all the pixels of the matrix can be read out via dedicated pads or through an analogue buffer.…”

Section: Pos(vertex2019)019mentioning

confidence: 99%

Recent depleted CMOS developments within the CERN-RD50 framework

Figueras¹

2020

Proceedings of the 28th International Workshop on Vertex Detectors — PoS(Vertex2019)

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Depleted CMOS sensors are groundbreaking position sensitive detectors that offer a competitive and cost-effective solution for a large range of particle tracking applications. In spite of their substantial advantages, these sensors require further research to become even more performant and meet the ever more demanding requirements of particle physics experiments planned for the near future. In this context, the CERN-RD50 collaboration has started a new R&D programme to study and develop depleted CMOS sensors as one of its main priorities. This article presents the depleted CMOS R&D programme within the CERN-RD50 collaboration. It describes the design aspects of the two prototype ASICs developed so far, which are in a 150 nm High Voltage-CMOS (HV-CMOS) process and manufactured on high resistivity substrates. The first prototype ASIC, named RD50-MPW1 and delivered after fabrication in April 2018, integrates a matrix of 50 μm x 50 μm pixels with all the analogue and digital readout electronics for column drain readout embedded in their sensing areas. The second prototype ASIC, named RD50-MPW2 and delivered after fabrication in January 2020, integrates a matrix of 60 μm x 60 μm pixels with analogue readout electronics to reduce the sensor response time. RD50-MPW2 incorporates new methods to optimise the leakage current of the sensor. The article discusses laboratory measurements of the performance evaluation of RD50-MPW1, while those of RD50-MPW2 will be published elsewhere.

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“…The depth of the depleted sensing volume can be approximately described by d ∝ √ ρ V , where d is the depletion depth, ρ is the resistivity of substrate and V the bias voltage. Thus, it is natural for CMOS pixels to utilize the high resistivity and high voltage features steadily offered by the commercial CMOS processes [10,11]. In this section, the two design approaches we have been following to achieve a fully depleted sensing layer are described.…”

Section: Sensor Design Approachesmentioning

confidence: 99%