Disturbance Relaxation for 3D Flash Memory

Chang, Yang-Lang; Chang, Yuan-Hao; Kuo, Tei-Wei; Li, Yung-Chun; Li, Hsiang-Pang

doi:10.1109/tc.2015.2451660

Cited by 12 publications

(5 citation statements)

References 36 publications

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“…Apart from the above circuit-level or chip-level hardware-based approaches, some software-based approaches can provide one part of the solution to mitigate the program disturbance. Y.-M. Chang et al proposed a programming method by dividing one physical block into two logical sub-blocks (referred to as reliable blocks) [29]. The selected pages to form a reliable block are not adjacent with each other.…”

Section: Improvement Of the Program Disturbmentioning

confidence: 99%

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

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The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

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Section: Improvement Of the Program Disturbmentioning

confidence: 99%

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

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“…Previous studies such as [22,26,27,[30][31][32][33][34][35][36] mainly analyze the failure of flash-based devices such as read disturbance, write disturbance, and endurance. Such failures are commonly reported in chip and device levels.…”

Section: Related Workmentioning

confidence: 99%

Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems

Ahmadian

Taheri

Asadi

2021

IEEE Trans. Emerg. Topics Comput.

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I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and nonvolatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss due to uncommitted write operations. Such configuration, however, may still experience data loss in the cache layer due to correlated failures in SSDs. To our knowledge, none of previous studies have investigated the reliability of SSD-based I/O caching schemes in enterprise storage systems.In this paper, we present a comprehensive analysis investigating the reliability of SSD-based I/O caching architectures used in enterprise storage systems under power failure and high-operating temperature. We explore variety of SSDs from top vendors and investigate the cache reliability in mirrored configuration. To this end, we first develop a physical fault injection and failure detection platform and then investigate the impact of workload dependent parameters on the reliability of I/O cache in the presence of two common failure types in data centers, power outage and high temperature faults. We implement an I/O cache scheme using an open-source I/O cache module in Linux operating system. The experimental results obtained by conducting more than twenty thousand of physical fault injections on the implemented I/O cache with different write policies reveal that the failure rate of the I/O cache is significantly affected by workload dependent parameters. Our results show that unlike workload requests access pattern, the other workload dependent parameters such as request size, Working Set Size (WSS), and sequence of the accesses have considerable impact on the I/O cache failure rate. We observe a significant growth in the failure rate in the workloads by decreasing the size of the requests (by more than 14X). Furthermore, we observe that in addition to writes, the read accesses to the I/O cache are subjected to failure in presence of sudden power outage (the failure mainly occurs during promoting data to the cache). In addition, we observe that I/O cache experiences no data failure upon high temperature faults.

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“…19 Each page is logically divided into a large "user area," which stores the user data and a small "out-of-band" area, which stores mapping information, metadata (eg, erase counter and page state) and ECC. 20,21 Flash memory operations: Flash memory allows program (write), read, and erase operations, which are managed by the FTL. 22 Reads/writes happen at page granularity whereas erase happens at block granularity.…”

Section: Flash Memory Architecture and Operationsmentioning

confidence: 99%

“…Each page is logically divided into a large “user area,” which stores the user data and a small “out‐of‐band” area, which stores mapping information, metadata (eg, erase counter and page state) and ECC. ()…”

Section: Introductionmentioning

confidence: 99%

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Alsalibi

Mittal

Al-Betar

et al. 2018

Concurrency and Computation

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Flash memory-based solid-state drives (SSDs) offer several attractive features and benefits compared to hard disk drive (HDD), such as shock resistance and better performance especially for random data access. Depending on the number of bits in each cell, Flash memory can be designed as single/multi/triple level cell (SLC/MLC/TLC), which have different performance, density, cost and write endurance characteristics. To bring the best of these together, several researchers have proposed designing SSD using hybrid SLC/MLC/TLC Flash memory. However, these SSDs also present several challenges such as buffer management, placement of hot/cold data in suitable portion, and intelligent garbage collection. Several recent techniques aim to address these challenges.In this paper, we present a survey of techniques for managing SSDs designed with SLC/MLC/TLC Flash memory. We classify the works on several axes to bring out their similarities and differences.We aim to synthesize the state-of-art progress in hybrid SSD management and also spark further research in this area. KEYWORDSflash translation layer, garbage collection, hybrid solid state disk, NAND flash memory, wear leveling INTRODUCTIONAs the amount of digital data continues to grow at an exponential rate and key applications become more data intensive, efficient storage architectures and management techniques have become more important than ever before. Conventionally, hard disk drive* has been used as a storage device; however, its limitations such as poor performance (especially for random accesses), higher form factor, and vulnerability to shocks and magnetic fields have encouraged researchers to explore its alternatives.Flash memory is a promising technology for designing storage devices due to its several attractive properties, eg, high performance and density, low power consumption, noise-free operation, and immunity to shocks and magnetic fields. 2-6 Also, its cost has been decreasing in recent years and it is expected to provide even better cost efficiency than HDD in near future. Based on the number of bits stored in each cell, Flash can be characterized as SLC (1 bit), MLC † (2 bit) and TLC (3 bits). As shown in Table 1, these cell types provide a spectrum of properties and trade-offs. Specifically, on going from SLC to MLC to TLC, the performance and write endurance decrease whereas density and cost efficiency improve.To achieve the best of these three cell types, hybrid SSD designs have been proposed, which use Flash memories of multiple cell types to improve performance, energy efficiency, and reliability. 16 However, these hybrid SSD designs also bring challenges, such as selection of relative proportion of SLC/MLC/TLC, efficient mapping/moving of hot/cold data to them, accounting for their disparate write endurance and density values, and

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Disturbance Relaxation for 3D Flash Memory

Cited by 12 publications

References 36 publications

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

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