Distributed active transformer-a new power-combining and impedance-transformation technique

Abstract

Abstract-In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-input and output matching has been fabricated using 0.35-m CMOS transistors.

A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS

“…The differential output stage also implies some additional aspects, besides the available double voltage swing, as each amplifier stage can utilize a lower power enhancement ratio [3,13] such that the efficiency can be higher than if a single-ended PA with a single L-match would have been used.…”

“…A more detailed analytical model of the transformer is the T-model, described in [13], where the efficiency was derived to be as follows (for optimum choice of L p and consideration of tuning capacitors [14]):…”

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

“…If this voltage directly appears across a 50 resistor, it delivers only 5.6 mW of power to the load. This major disparity can be captured by the very large power enhancement ratio (PER) defined as the ratio of the required power into the load, (e.g., 3.1 W for GSM) to the maximum power directly deliverable to the load by the transistor assuming the same voltage swing, (e.g., 5.6 mW for a single 130 nm drive NMOS), i.e., [18] (1) This necessitates the use of an impedance matching network that can present a smaller impedance to the transistor, so it can deliver a larger power by driving a lower impedance load at a lower voltage and higher current swing.…”

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“…This reduces the size of each transistor, and hence the compact lumped model of the transistor becomes more accurate. Division of the power generation core into smaller cells has additional advantages in terms of uniform on-chip heat distribution and also relaxed impedance transformation ratio [33], but necessitates the use of a power-combining structure. As shown in Fig.…”