Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

Koo, Heon-Mo; Mishra, Prabhat; Bhadra, Jayanta; Abadir, Magdy S.

doi:10.1109/mtv.2006.10

Cited by 10 publications

(4 citation statements)

References 7 publications

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“…In Piparazzi [10], a model of microarchitectural processor and the user's specification are converted into a constraint satisfaction problem (CSP) and the dedicated CSP solver is used to construct an actual test program. Many techniques have been proposed for directed test program generation based on an instruction tree traversal [11], micro-architectural coverage [12,13], and functional coverage using Bayesian networks [2]. Recently, Gluska [14] described the need for coverage directed test generation in coverage-oriented verification of the Intel Merom microprocessor.…”

Section: Related Workmentioning

confidence: 99%

Automated Generation of Directed Tests

Chen

Qin

Koo

et al. 2012

System-Level Validation

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Increasing complexity combined with decreasing time-to-market requirement make the functional validation a major bottleneck in the HW/SW design flow. As a most widely used validation method, simulation employs tests in the following three categories: random, constrained-random tests, and directed tests. Random and constrained-random testing [1] are easy to implement; nevertheless, it is hard to guarantee the convergence to the testing target (i.e., functional coverage). In contrast, directed testing [2] uses fewer tests to obtain the required functional coverage since it exploits the design structure information. By applying the directed tests, the validation effort can be drastically reduced. However, most directed test generation methods assume the expert knowledge of the design under validation (DUV). Due to the inevitable human intervention, current directed test generation methods are laborious and error-prone. Therefore, it is necessary to develop efficient techniques to automate the process of directed test generation.Model checking [3] is a formal method which can verify whether a temporal property is satisfied for a finite state concurrent system. In model checking, a design is modeled as a state transition graph, called a Kripke structure [3], which is a fourtuple model M = (S, S 0 , R, L). S is a finite set of states. S 0 is a set of initial states, where S 0 ⊆ S. R : S → S is a transition relation between states, where for every state s ∈ S, there is a state s ∈ S such that the state transition (s, s ) ∈ R. L : S → 2 AP is the labeling function to mark each state with a set of atomic propositions (AP) that hold in that state. Properties are expressed as linear temporal logic (LTL) and computational tree logic (CTL) formulas to describe expected design behaviors. For a formal model M of the design and a property p, the model checking is to find whether all states in S satisfy p or not. If there does not exist a reachable error state from initial states, the design satisfies the property, i.e., M |= p. Otherwise, the property does not hold for the design, and a variable assignment trace (counterexample) from an initial state to the error state will be reported. Such a trace can be used as a test to activate the scenario described by the negation of the checked property p.M. Chen et al., System-Level Validation,

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Section: Related Workmentioning

confidence: 99%

Automated Generation of Directed Tests

Chen

Qin

Koo

et al. 2012

System-Level Validation

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“…All this makes it possible to use composite justification for single and multiple faults in MOS circuits, by applying some necessary modifications. The logic modeling of various MOS-circuit faults has been thoroughly discussed in [10]- [13]. Figure 2 shows an NMOS and a PMOS transistor.…”

Section: Switch-level Faultsmentioning

confidence: 99%

Switch-Level Test Calculation for CMOS Circuits

Sziray

2009

2009 10th International Workshop on Microprocessor Test and Verification

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The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck short (short circuit) behavior. In this paper only combinational logic is taken into consideration. The computations are performed at the transistor level directly, i. e., by using the original transistor schematic solely, without any logic conversion. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program.

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“…We have developed novel design and property decomposition techniques [Koo and Mishra 2006a] as well as SAT-based bounded model-checking techniques [Koo and Mishra 2006b] to address the state-space explosion problem in test generation. Our initial study using the Freescale e500 processor [FreeScale 2005] shows promising results [Koo et al 2006] in applying decompositional model-checking-based test generation on industrial microprocessors.…”

Section: Algorithm 2 Test Program Generationmentioning

confidence: 99%

Specification-driven directed test generation for validation of pipelined processors

Mishra

Dutt

2008

ACM Trans. Des. Autom. Electron. Syst.

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Functional validation is a major bottleneck in pipelined processor design due to the combined effects of increasing design complexity and lack of efficient techniques for directed test generation. Directed test vectors can reduce overall validation effort, since shorter tests can obtain the same coverage goal compared to the random tests. This article presents a specification-driven directed test generation methodology. The proposed methodology makes three important contributions. First, a general graph model is developed that can capture the structure and behavior (instruction set) of a wide variety of pipelined processors. The graph model is generated from the processor specification. Next, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, we propose two complementary test generation techniques: test generation using model checking, and test generation using template-based procedures. These test generation techniques accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate several orders-of-magnitude reduction in overall validation effort by drastically reducing both test-generation time and number of test programs required to achieve a coverage goal. ACM Reference Format:Mishra, P. and Dutt, N. 2008. Specification-driven directed test generation for validation of pipelined processors.

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Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

Cited by 10 publications

References 7 publications

Automated Generation of Directed Tests

Automated Generation of Directed Tests

Switch-Level Test Calculation for CMOS Circuits

Specification-driven directed test generation for validation of pipelined processors

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