Specification-driven directed test generation for validation of pipelined processors

Abstract

Functional validation is a major bottleneck in pipelined processor design due to the combined effects of increasing design complexity and lack of efficient techniques for directed test generation. Directed test vectors can reduce overall validation effort, since shorter tests can obtain the same coverage goal compared to the random tests. This article presents a specification-driven directed test generation methodology. The proposed methodology makes three important contributions. First, a general graph model is developed that can capture the structure and behavior (instruction set) of a wide variety of pipelined processors. The graph model is generated from the processor specification. Next, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, we propose two complementary test generation techniques: test generation using model checking, and test generation using template-based procedures. These test generation techniques accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate several orders-of-magnitude reduction in overall validation effort by drastically reducing both test-generation time and number of test programs required to achieve a coverage goal. ACM Reference Format:Mishra, P. and Dutt, N. 2008. Specification-driven directed test generation for validation of pipelined processors.

MicroTESK: An Extendable Framework for Test Program Generation

“…In [5], a method for directed test program generation has been proposed. It takes detailed microprocessor specifications written in the EXPRESSION language [9] and translates them into the SMV (Symbolic Model Verifier) description [10].…”

“…All of them can be subdivided in the following categories: (1) random generation [3], (2) combinatorial generation [2], (3) template-based generation [4] and (3) model-based generation [5]. The thing is that there is no a "silver bullet", which can effectively "fight" against all kinds of testing tasks.…”

Reuse of System-Level Validation Efforts

“…3, property falsification in model checking is promising for automated generation of directed test [21,22]. The algorithm has two inputs: (i) model of the design in SMV specification and (ii) a set of properties derived from the specified fault models described in Sect.…”

Generating test programs to cover pipeline interactions

“…Zhu et al [11] synthesize directed tests from a high-level description to test the bypass paths in a pipelined processor. Mishra and Dutt [7] exploit test program templates for canonical events like pipeline hazards and exceptions. However the template generation is not automated, and this has to be done manually by the designer.…”