Switch-Level Test Calculation for CMOS Circuits

Abstract

The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck short (short circuit) behavior. In this paper only combinational logic is taken into consideration. The computations are performed at the transistor level directly, i. e., by using the original transistor schematic solely, without any logic conversion. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program.

Computational complexity in test-generation algorithms

“…Furthermore, it may also be expected that the thesis of minimal complexity applies in general to any categories of test-generation problems for logic circuits, independent of the modeling level and fault types [12], [16]. From this it follows that the solutions to be obtained are also of exponential time.…”