Direct Gradient Calculation: Simple and Variation‐Tolerant On‐Chip Training Method for Neural Networks

Abstract

On‐chip training of neural networks (NNs) is regarded as a promising training method for neuromorphic systems with analog synaptic devices. Herein, a novel on‐chip training method called direct gradient calculation (DGC) is proposed to substitute conventional backpropagation (BP). In this method, the gradients of a cost function with respect to the weights are calculated directly by sequentially applying a small temporal change to each weight and then measuring the change in cost value. DGC achieves a similar accuracy to that of BP while performing a handwritten digit classification task, validating its training feasibility. In particular, DGC can be applied to analog hardware‐based convolutional NNs (CNNs), which is considered to be a challenging task, enabling appropriate on‐chip training. A hybrid method is also proposed that efficiently combines DGC and BP for training CNNs, and the method achieves a similar accuracy to that of BP and DGC while enhancing the training speed. Furthermore, networks utilizing DGC maintain a higher level of accuracy than those using BP in the presence of variations in hardware (such as synaptic device conductance and neuron circuit component variations) while requiring fewer circuit components.

Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training

“…To address this, additional on-chip training is conducted after weight transfer, as on-chip training is known to find an optimal point under the pressure of variation. [17] Unlike previously reported hybrid training approaches, [44] which utilize the same voltage for weight transfer and on-chip training, the Side Path device employs weak PGM/ERS pulses for on-chip training to overcome the following two issues observed with strong PGM/ERS pulses: 1) increased energy consumption due to repeated high-voltage operations, and 2) endurance failures, as shown in Figure 4i. The use of weak PGM/ERS pulses mitigates these issues, as the Side Path device can modulate weight at low voltages, unlike traditional Flash or A/N/O devices.…”

“…[15] On the other hand, the second method is on-chip training, where weight values of synaptic devices are updated during runtime using additional circuitry. [16,17] The approach allows the network to adapt to device variations during the training phase, providing more robust performance. However, since on-chip training requires repeated weight updates, the synaptic devices require a low program (PGM) / erase (ERS) energy for the low-power operation of the overall system.…”

Si‐Based Dual‐Gate Field‐Effect Transistor Array for Low‐Power On‐Chip Trainable Hardware Neural Networks

“…[15][16][17] HNNs can be categorized into two types: off-chip trained HNNs and on-chip trainable HNNs. [18] In off-chip trained HNNs, the weight values are trained in software and transferred to the synaptic array. [19] Consequently, only forward inference of a neural network is conducted in the hardware.…”