Abstract:Herein, dual‐gate field‐effect transistors (DG FETs) fabricated on Si substrate and a corresponding NOR‐type array designed for low‐power on‐chip trainable hardware neural networks (HNNs) are presented. The fabricated DG FET exhibits notable endurance characteristics, with the subthreshold swing remaining consistently within a 2.45% range of change and ΔV
th per cycle maintaining stability at 4.5% over repetitive program and erase operations, up to 104 cycles. Furthermore, a multilevel characteristic is achiev… Show more
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