Digital Systems Power Management for High Performance Mixed Signal Platforms

Kapoor, Ajay; Groot, Cas; Piqué, Gerard Villar; Fatemi, Hamed; Echeverri, Juan; Sevat, L.; Vertregt, M.; Meijer, Maurice; Sharma, Vibhu Saujanya; Pu, Yu; Gyvez, José Pineda de

doi:10.1109/tcsi.2014.2304662

Cited by 15 publications

(4 citation statements)

References 41 publications

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“…Today's design tools are optimised for synthesizing clock trees on a single chip and at most to the area of a motherboard. Furthermore, it has been reported [13] that in modern chips, in order to conform to timing constraints, an elaborate clock tree is synthesised such that as much as 40% of the total power consumption is utilized by just the clock-tree. An alternate solution would be to use a crystal oscillator in each meta-atom, and use a phaselocked loop to bring all clocks in sync.…”

Section: • Timing Constraintsmentioning

confidence: 99%

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

Petrou

Karousios

Georgiou

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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Metamaterials and metasurfaces have given possibilities for manipulating electromagnetic (EM) waves that in the past would have seemed impossible. The majority of metasurface designs are suitable for a particular frequency and angle of incidence. One long-sought objective is the design of programmable metasurfaces to dynamically manipulate a variety of incoming EM frequencies and angles. In order to do this, a large-scale mesh of networked chips are required below the metasurface, which apart from adapting electrical impedance properties, also communicate with each other, thus relaying information about meta-atom settings, as well as forwarding possible distributed measurements taken. This paper describes why an asynchronous mixed-signal ASIC is advantageous for the control of scalable, EM absorbing, metasurfaces.

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Section: • Timing Constraintsmentioning

confidence: 99%

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

Petrou

Karousios

Georgiou

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Under low V DD , high temperature and large number of cells per RBL, it is pretty difficult to deliver equation (1). This is due to the fact that these circumstances makeI on/ I off ratio small, as mentioned above.…”

Section: Bl Leakage In Conventional 8t Srams and Existing Leakage Compensation Techniquesmentioning

confidence: 99%

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

Tuan

Lee

Wang

et al. 2016

IEEE J. Solid-State Circuits

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In sub/near-threshold operation, SRAMs suffer from considerable bit-line swing degradation when the data pattern of a column is skewed to "1" or "0". The worst scenariosregarding this problemoccur when the currently readSRAM cell has different data compared to the rest cells onthe same column. In this work, we overcome this challenge by using a column-based randomization engine(CBRE).ThisCBREcircuit randomizesdata stored to SRAM. This makes distribution of "1" and "0" in each column close to 50%, significantlyincreasingbit-line swing. To further improve the bit-line swing, we employ bit-line boost biasing and dynamic bit-line keeper schemes. Based on the mentioned techniques, we fabricateda 256 rows × 128 columns (32Kb)8T SRAM array in 65 nm CMOS technology.In our silicon measurement, the SRAM array shows successful 200mVoperation at room temperate, where energy consumption and access time are1 pJ and 2.5 µs, respectively.

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“…ltra-low power circuits are highly demanded in many green computing systems where ultralow voltage operation offers better energy efficiency with moderation in performance [1,2]. However, ultra-low voltage operation suffers from degraded noise margin and large performance variations due to aggressively scaled supply voltages [3]. One of the most challenging functional blocks in ultra-low voltage operation is an SRAM because of various U design parameters such as stability, write margin, sensing margin, and bitline leakage.…”

Section: Introductionmentioning

confidence: 99%

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Kim

Lee

Tuan

2018

Solid-State Electronics

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Digital Systems Power Management for High Performance Mixed Signal Platforms

Cited by 15 publications

References 41 publications

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

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Digital Systems Power Management for High Performance Mixed Signal Platforms

Cited by 15 publications

References 41 publications

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

Contact Info

Product

Resources

About

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation